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27th PATMOS 2017: Thessaloniki, Greece
- 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017, Thessaloniki, Greece, September 25-27, 2017. IEEE 2017, ISBN 978-1-5090-6462-5
- Yuxin Qian, Cong Hao, Takeshi Yoshimura:
3D-IC signal TSV assignment for thermal and wirelength optimization. 1-8 - Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Nestor E. Evmorfopoulos, George Dimitriou, Georgios I. Stamoulis:
Placement-based SER estimation in the presence of multiple faults in combinational logic. 1-6 - Evangelos Vasilakis, Ioannis Sourdis, Vassilis Papaefstathiou, Antonis Psathakis, Manolis G. H. Katevenis:
Modeling energy-performance tradeoffs in ARM big.LITTLE architectures. 1-8 - Esteve Amat
, Antonio Calomarde
Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level. 1-6 - Erwan Moreac, Johann Laurent, Pierre Bomel, André Rossi, Emmanuel Boutillon, Maurizio Palesi:
Energy aware Networks-on-Chip cortex inspired communication. 1-8 - Haotian Zhu, Jianping Hu, Huishan Yang, Yang Xiong, Tingfeng Yang:
A topology optimization method for low-power logic circuits with dual-threshold independent-gate FinFETs. 1-6 - Dalibor Biolek, Zdenek Biolek, Viera Biolková:
Memristive two-ports. 1-4 - Daniele Jahier Pagliari
Optimal content-dependent dynamic brightness scaling for OLED displays. 1-6 - Moritz Weißbrich, Guillermo Payá Vayá, Lukas Gerlach
FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework. 1-8 - Ayrat Galisultanov, Yann Perrin
Capacitive adiabatic logic based on gap-closing MEMS devices. 1-6 - Lotta Romhildt, Felix Zorgiebel, Bergoi Ibarlucea
Human α-thrombin detection platform using aptamers on a silicon nanowire field-effect transistor. 1-4 - John Reuben
Memristive logic: A framework for evaluation and comparison. 1-8 - Frederic Roger, Anderson Pires Singulani, Jong Mun Park:
Optical sensor process variability in a 0.18 μm high voltage CMOS technology. 1-6 - Carol de Benito
An analytical delay model for ReRAM memory cells. 1-6 - Yunpeng Cai, Anand Savanth
Evaluation and analysis of single-phase clock flip-flops for NTV applications. 1-6 - Stephan Menzel, Rainer Waser, Anne Siemon, Camilla La Torre, M. Schulten, Alon Ascoli, Ronald Tetzlaff
On the origin of the fading memory effect in ReRAMs. 1-5 - Md Shahidul Alam, Alberto García Ortiz
An FPGA-based thermal emulation framework for multicore systems. 1-6 - Dominik Macko
Rapid power-management exploration using post-processing of the system-level simulation results. 1-6 - Nicolo Zagni
Variability and sensitivity to process parameters variations in InGaAs dual-gate ultra-thin body MOSFETs: A scaling perspective. 1-5 - Michail Noltsis, Eleni Maragkoudaki, Dimitrios Rodopoulos, Francky Catthoor, Dimitrios Soudris:
Failure probability of a FinFET-based SRAM cell utilizing the most probable failure point. 1-8 - Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale:
Robustness of power analysis attack resilient adiabatic logic: WCS-QuAL under PVT variations. 1-8 - Leonidas Katselas, Hailong Jiao, Angelos Athanasiadis
Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs. 1-8 - Nikolaos Kefalas
High-throughput FPGA implementation of the CCSDS 122.0-B-1 compression standard. 1-8 - Antonio Pullini, Davide Rossi, Germain Haugou, Luca Benini
μDMA: An autonomous I/O subsystem for IoT end-nodes. 1-8 - Jingjing Guo, Min Wang, Jizhe Zhu, Xinning Liu, Jun Yang:
Analytical hold timing fixing for sub-threshold circuit based on its lognormal distribution. 1-8 - Adrian Wheeldon
Power proportional adder design for Internet of Things in a 65 nm process. 1-6 - Nils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel:
Timing modeling at RT-level by separation of design- and stress related aging impacts. 1-6 - Sunil Malipatlolla, Ahmet Unutulmaz, Domenik Helms, Wolfgang Nebel:
User dependent aging prediction model for automotive controllers with power electronics. 1-6 - Pasquale Davide Schiavone, Francesco Conti, Davide Rossi, Michael Gautschi, Antonio Pullini, Eric Flamand, Luca Benini
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications. 1-8 - Thanasin Bunnam
Pulse controlled memristor-based delay element. 1-8 - Daniel Wust, Mehrdad Biglari, Johannes Knödtel, Marc Reichenbach
Prototyping memristors in digital system with an FPGA-based testing environment. 1-7 - Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini:
Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology. 1-8 - Konstantinos Tatas
3DBUFFBLESS: A novel buffered-bufferless hybrid router for 3D Networks-on-Chip. 1-8 - Milan Babic, Milos Krstic
A substrate noise reduction methodology based on power domain separation of GALS subcomponents. 1-6 - Panagiotis N. Smyrlis, Dimosthenis C. Tsouros
Parallelization and energy evaluation of interframe compression technique for video images - QSDPCM. 1-8 - Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir:
Parasitic effects on memristive logic architecture. 1-5 - Dimosthenis Masouros, Ioannis Bakolas, Vasileios Tsoutsouras, Kostas Siozios
From edge to cloud: Design and implementation of a healthcare Internet of Things infrastructure. 1-6 - Stylianos-Georgios Papadopoulos, Vasileios Gerakis, Yiorgos Tsiatouhas
Oscillation-based technique for post-bond parallel testing and diagnosis of multiple TSVs. 1-6 - Khaled Al-Maaitah
Approximate adder segmentation technique and significance-driven error correction. 1-6 - Lei Li, Michael Gautschi, Luca Benini:
Approximate DIV and SQRT instructions for the RISC-V ISA: An efficiency vs. accuracy analysis. 1-8 - Basireddy Karunakar Reddy
Empirical CPU power modelling and estimation in the gem5 simulator. 1-8 - Thomas Mesquida, Alexandre Valentian, David Bol, Edith Beigné
Architecture exploration of a fixed point computation unit using precise timing spiking neurons. 1-8 - Ardalan Najafi
A fair comparison of adders in stochastic regime. 1-6 - Rafailia-Eleni Karamani, Vasileios G. Ntinas
1-D memristor-based cellular automaton for pseudo-random number generation. 1-6 - Islam A. K. M. Mahfuzul
Effect of supply voltage on random telegraph noise of transistors under switching condition. 1-8 - Savvas Sava
Fault-tolerant routing methodology for Networks-on-Chip. 1-3 - Lennart Bamberg
Edge effect aware crosstalk avoidance technique for 3D integration. 1-8 - Steve Ngueya W., Julien Mellier, Stephane Ricard, Jean-Michel Portal, Hassen Aziza:
High voltage recycling scheme to improve power consumption of regulated charge pumps. 1-5
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