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1. PARBASE 1990: Miami Beach, Florida
- Naphtali Rishe, Shamkant B. Navathe, Doron Tal:
Parallel Architectures (Postconference PARBASE-90). IEEE Computer Society 1990, ISBN 0-8186-9166-2 - Doron Tal, Naphtali Rishe, Shamkant B. Navathe, Scott Graham:
On Parallel Architectures. PARBASE / Architectures 1990: 1-17 - C. A. R. Hoare:
A Theory of Conjunction and Concurrency. 18-30 - Mohan Ahuja, Kannan Varadhan, Amitabh Sinha:
Flush Message Passing in Communicating Sequential Processes. 31-47 - Hessa Al-Jaber, Shmuel Rotenstreich:
Fault Tolerance of Message Delivery with Cascading Copies. 48-67 - Suresh Chalasani, Anujan Varma:
Analysis and Simalation of Multistage Interconnection Networks under Non-Uniform Traffic. 68-87 - Hyeong-Ah Choi, Bhagirath Narahari, Shmuel Rotenstreich, Abdou Youssef:
Scheduling on Parallel Processing Systems Using Parallel Primitives. 88-107 - Arthur F. Dickinson, Ratan K. Guha:
Space Efficient List Merging on a Multiprocessor Ring. 108-123 - Jai Eun Jang:
An Optimal Fault-Tolerant Broadcasting Algorithm for a Cube-Connected Cycles Multiprocessor. 124-140 - V. Prasad Krothapalli, P. Sadayappan:
Dynamic Scheduling of DOACROSS Loops for Multiprocessors. 141-160 - Constantine N. K. Osiakwan, Selim G. Akl:
A Perfect Speedup Parallel Algorithm for the Assignment Problem on Complete Weighted Bipartite Graphs. 161-180 - Behrooz Parhami:
Scalable Architectures for VLSI-Based Associative Memories. 181-200 - Manohar Rao, Zary Segall:
Implementation and Evaluation of a Parallel PMS Simulator. 201-215 - T. D. Roziner:
Systolic Macropipelines for Multidimensional Fourier Transforms. 216-230 - Peter J. Varman, Balakrishna R. Iyer, Donald J. Haderle:
Parallel Merging on Shared and Distributed Memory Computers. 231-249 - Jie Wu, Eduardo B. Fernández
:
The Extended G-Network, a Fault-Tolerant Interconnection Network for the Multiprocessors. 250-259 - Qing Yang:
Performance Analysis of a Cache-Coherent Multiprocessor Based on Hierarchical Multiple Buses. 260-275 - Qing Yang, Ravi Raja:
Design and Analysis of Multiple-Bus Arbiters with Different Priority Schemes. 276-295
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