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ISVLSI 2019: Miami, FL, USA
- 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, FL, USA, July 15-17, 2019. IEEE 2019, ISBN 978-1-7281-3391-1
Session 01: Digital Circuits and FPGA Based Designs I
- Xiaoru Xie, Fangxuan Sun, Jun Lin, Zhongfeng Wang:
Fast-ABC: A Fast Architecture for Bottleneck-Like Based Convolutional Neural Networks. 1-6 - Yiming Hu, Shuang Liang, Jincheng Yu, Yu Wang, Huazhong Yang:
On-Chip Instruction Generation for Cross-Layer CNN Accelerator on FPGA. 7-12 - Yao Chen
, Kai Zhang, Cheng Gong
T-DLA: An Open-source Deep Learning Accelerator for Ternarized DNN Models on Embedded FPGA. 13-18
Session 02: Special Session: FPGA Accelerator Design and Optimization I
- Arish S
Optimization of Convolutional Neural Networks on Resource Constrained Devices. 19-24 - Xinyi Zhang, Weiwen Jiang, Yiyu Shi, Jingtong Hu:
When Neural Architecture Search Meets Hardware Implementation: from Hardware Awareness to Co-Design. 25-30 - Chi Fung Brian Fong, Jiandong Mu, Wei Zhang:
A Cost-Effective CNN Accelerator Design with Configurable PU on FPGA. 31-36
Session 03: System Design and Security I
- Ugo Mureddu, Brice Colombier, Nathalie Bochard, Lilian Bossuet, Viktor Fischer:
Transient Effect Ring Oscillators Leak Too. 37-42 - Alex Ayling
Not All Feed-Forward MUX PUFs Generate Unique Signatures. 43-48 - Johan Marconot, David Hély, Florian Pebay-Peyroula:
SPN-DPUF: Substitution-Permutation Network Based Secure Circuit for Digital PUF. 49-54
Session 04: Special Session: FPGA Accelerator Design and Optimization II
- Xinzhe Liu, Fupeng Chen, Yajun Ha:
Area Efficient Box Filter Acceleration by Parallelizing with Optimized Adder Tree. 55-60 - Feng Xiong, Fengbin Tu, Shouyi Yin, Shaojun Wei:
Towards Efficient Compact Network Training on Edge-Devices. 61-67 - Ashutosh Dhar, Sitao Huang, Jinjun Xiong
Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads. 68-75
Session 05: Computer-Aided Design and Verification I
- Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Integer Dividers: Division by a Constant. 76-81 - Mehrnoosh Raoufi, Quan Deng, Youtao Zhang, Jun Yang:
PageCmp: Bandwidth Efficient Page Deduplication through In-memory Page Comparison. 82-87 - Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi:
An ESL Environment for Modeling Electrical Interconnect Faults. 88-93 - Cheng-Wei Tai, Rung-Bin Lin:
Morphed Standard Cell Layouts for Pin Length Reduction. 94-99
Session 06: Special Session: NVM Based Architecture and System I
- Sébastien Ollivier, Donald Kline Jr., Kawsher A. Roxy, Rami G. Melhem, Sanjukta Bhanja, Alex K. Jones
The Power of Orthogonality. 100-102 - Mimi Xie, Yawen Wu, Zhenge Jia
In-memory AES Implementation for Emerging Non-Volatile Main Memory. 103 - Vamsee Reddy Kommareddy, Clayton Hughes
Investigating Fairness in Disaggregated Non-Volatile Memories. 104-110 - Hao Cai, Honglan Jiang, Menglin Han, Zhaohao Wang, You Wang, Jun Yang, Jie Han, Leibo Liu
Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction. 111-115
Session 07: Computer-Aided Design and Verification II
- Salma Hesham, Diana Goehringer, Mohamed A. Abd El Ghany
Dark-Silicon Inspired Energy Efficient Hierarchical TDM NoC. 116-121 - Anup Gangwar, Zheng Xu, Nitin Kumar Agarwal, Ravishankar Sreedharan, Ambica Prasad:
Traffic Driven Automated Synthesis of Network-on-Chip from Physically Aware Behavioral Specification. 122-127 - Jong Bin Lim, Deming Chen:
Automated Communication and Floorplan-Aware Hardware/Software Co-Design for SoC. 128-133 - Mohammed M. Alawad, Georgia D. Tourassi:
Computationally Efficient Learning of Quality Controlled Word Embeddings for Natural Language Processing. 134-139
Session 08: Circuit, Reliability and Fault Tolerance I
- M. Mohamed Asan Basiri
Formal Hardware Verification of InfoSec Primitives. 140-145 - Taehwan Kim, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi:
SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage. 146-151 - Mingze Gao, Qian Wang, Gang Qu:
Energy and Error Reduction using Variable Bit-width Optimization on Dynamic Fixed Point Format. 152-157 - Anderson Luiz Sartor, Pedro Henrique Exenberger Becker, Stephan Wong, Radu Marculescu, Antonio Carlos Schneider Beck:
Machine Learning-Based Processor Adaptability Targeting Energy, Performance, and Reliability. 158-163
Session 09: VLSI for Applied and Future Computing Technology I
- Osman Elgawi, A. M. Mutawa
Energy-Efficient Embedded Inference of SVMs on FPGA. 164-168 - Pankaj Bhowmik, Md Jubaer Hossain Pantho, Sujan Kumar Saha, Christophe Bobda:
A Reconfigurable Layered-Based Bio-Inspired Smart Image Sensor. 169-174 - Sunil R., Siddharth R. K.
An Asynchronous Analog to Digital Converter for Video Camera Applications. 175-180 - Zheyu Liu, Zichen Fan, Qi Wei, Xing Wu, Fei Qiao, Ping Jin, Xinjun Liu, Chengliang Liu, Huazhong Yang:
Design of Switched-Current Based Low-Power PIM Vision System for IoT Applications. 181-186
Session 10: Special Session: Neuromorphic Computing and Emerging Technologies
- Ruizhe Cai, Xiaolong Ma, Olivia Chen
IDE Development, Logic Synthesis and Buffer/Splitter Insertion Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits. 187-192 - Adarsha Balaji, Anup Das
A Framework for the Analysis of Throughput-Constraints of SNNs on Neuromorphic Hardware. 193-196 - Shaahin Angizi, Zhezhi He, Dayane Alfenas Reis
Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach? 197-202 - Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang, Youguang Zhang, Weisheng Zhao:
Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration. 203-206
Poster Session
- Gopabandhu Hota, Hardik Agrawal, Mrigank Sharad:
An Area Effective Programmable Front-end Amplifier for Neural Signal Acquisition. 207-211 - Sudipta Paul, Pritha Banerjee
Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification. 212-217 - Ning-Chi Huang, Yu-Guang Chen, Kai-Chiang Wu:
Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs. 218-223 - Walter Lau Neto, Xifan Tang, Max Austin, Luca G. Amarù, Pierre-Emmanuel Gaillardon:
Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs. 224-229 - Xiangyu Chen
Design of a CMOS Broadband Transimpedance Amplifier with Floating Active Inductor. 230-234 - Prashansa Mukim, Aditya Dalakoti, David McCarthy, Brandon Pon, Carrie Segal, Merritt Miller, James F. Buckwalter, Forrest Brewer
Distributed Pulse Rotary Traveling Wave VCO: Architecture and Design. 235-240 - Sebastian Pointner, Oliver Frank, Christoph Hazott, Robert Wille:
Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows. 241-246 - Zheng Xu, Jacob Abraham:
Design of a Safe Convolutional Neural Network Accelerator. 247-252 - Yang Sun, Spencer K. Millican:
Test Point Insertion Using Artificial Neural Networks. 253-258 - Jonas Gava
Evaluation of Compilers Effects on OpenMP Soft Error Resiliency. 259-264 - Ann Gordon-Ross, Saleh Abdel-Hafeez, Mohamad Hammam Alsafrjalani:
A One-Cycle FIFO Buffer for Memory Management Units in Manycore Systems. 265-270 - Timothy J. Baker
Impact of Autocorrelation on Stochastic Circuit Accuracy. 271-277 - Brett Mathis, James E. Stine
A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter. 278-283 - Henrique Placido, Ricardo Reis:
Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm. 284-289 - Nicolás Wainstein, Tamir Tsabari, Yarden Goldin, Eilam Yalon
A Dual-Band CMOS Low-Noise Amplifier using Memristor-Based Tunable Inductors. 290-295 - Pampa Howladar, Pranab Roy, Hafizur Rahaman:
Micro-electrode-dot Array Based Biochips : Advantages of Using Different Shaped CMAs. 296-301 - Shichao Yu
An Improved Automatic Hardware Trojan Generation Platform. 302-307 - Cyril Bresch, David Hély, Stéphanie Chollet, Ioannis Parissis:
TrustFlow: A Trusted Memory Support for Data Flow Integrity. 308-313 - Siva Nishok Dhanuskodi, Daniel E. Holcomb:
Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel Susceptibility. 314-319 - Abhishek Vashist, Andrew Keats, Sai Manoj Pudukotai Dinakarrao
Securing a Wireless Network-on-Chip Against Jamming Based Denial-of-Service Attacks. 320-325 - Yu Zou, Mingjie Lin:
FAST: A Frequency-Aware Skewed Merkle Tree for FPGA-Secured Embedded Systems. 326-331 - Adnan Siraj Rakin, Deliang Fan:
Defense-Net: Defend Against a Wide Range of Adversarial Attacks through Adversarial Detector. 332-337 - Yasaswy Kasarabada, Sudheer Ram Thulasi Raman, Ranga Vemuri
Deep State Encryption for Sequential Logic Circuits. 338-343
Student Research Forum
- Amina Annagrebah, E. Bechetoille, I. B. Laktineh, H. Chanal, P. Russo, H. Mathez:
A Multi-phase Time-to-Digital Converter Differential Vernier Ring Oscillato. 344-347 - Shivam Swami, Kartik Mohanram:
ASSET: Architectures for Smart Security of Non-Volatile Memories. 348-353 - Arman Roohi, Ronald F. DeMara:
IRC Cross-Layer Design Exploration of Intermittent Robust Computation Units for IoTs. 354-359 - Edgard Muñoz-Coreas, Himanshu Thapliyal
Design of Quantum Circuits for Cryptanalysis and Image Processing Applications. 360-365 - Satya Venkata Sandeep Avvaru, Keshab K. Parhi
Effect of Loop Positions on Reliability and Attack Resistance of Feed-Forward PUFs. 366-371 - Yunxiang Zhang, Xiaokun Yang, Lei Wu, Jean Andrian:
A Case Study On Approximate FPGA Design With an Open-Source Image Processing Platform. 372-377 - Kevin Vaca, Archit Gajjar
Real-Time Automatic Music Transcription (AMT) with Zync FPGA. 378-384
Session 11: Digital Circuit and FPGA Based Designs II
- Tongxin Yang, Toshinori Sato
An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area. 385-390 - Matthew Gaalswyk, James E. Stine
A Low-Power Recurrence-Based Radix 4 Divider Using Signed-Digit Addition. 391-396 - Ling Qiu, Ziji Zhang, Jon Calhoun, Yingjie Lao:
Towards Data-Driven Approximate Circuit Design. 397-402
Session 12: Special Session: Explorations in Energy-Efficient Computing for IoT Applications I
- Soheil Salehi
MRAM-Based Stochastic Oscillators for Adaptive Non-Uniform Sampling of Sparse Signals in IoT Applications. 403-408 - Hiroki Koyasu, Yasuhiro Takahashi
Evaluation of Power Analysis Attacks on Cryptographic Circuit Using Adiabatic Logic. 409-413 - Himanshu Thapliyal
Approximate Energy Recovery 4-2 Compressor for Low-Power Sub-GHz IoT Applications. 414-418
Session 13: Emerging and Post-CMOS Technologies I
- Sarit Chakraborty, Susanta Chakraborty:
Routing Performance Optimization for Homogeneous Droplets on MEDA-based Digital Microfluidic Biochips. 419-424 - Ling-Yen Song, Yu-Ying Li, Yung-Chun Lei, Juinn-Dar Huang
Time-Constrained Sample Preparation Algorithm for Reactant Minimization on Digital Microfluidic Biochips. 425-430 - Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits. 431-436
Session 14: Special Session: Explorations in Energy-Efficient Computing for IoT Applications II
- Xunzhao Yin, Dayane Alfenas Reis
Ferroelectric FET Based TCAM Designs for Energy Efficient Computing. 437-442 - Yasuhiro Takahashi
Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function. 443-446 - Zheyu Liu, Erxiang Ren
A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications. 447-452
Session 15: VLSI for Applied and Future Computing Technology II
- Jingyan Fu
Linear Optimization for Memristive Device in Neuromorphic Hardware. 453-458 - Md Jubaer Hossain Pantho, Pankaj Bhowmik, Christophe Bobda:
Neuromorphic Image Sensor Design with Region-Aware Processing. 459-464 - Arash Fayyazi, Souvik Kundu
CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity. 465-470
Session 16: System Design and Security II
- Luciano L. Caimi
Security in Many-Core SoCs Leveraged by Opaque Secure Zones. 471-476 - Siavoosh Payandeh Azad, Gert Jervan
CAESAR-MPSoC: Dynamic and Efficient MPSoC Security Zones. 477-482 - Zhiming Zhang, Qiaoyan Yu:
Modeling Hardware Trojans in 3D ICs. 483-488
Session 17: Circuit, Reliability and Fault Tolerance II
- Zengchao Yan, Jun Lin, Zhongfeng Wang:
A Low-Complexity RS Decoder for Triple-Error-Correcting RS Codes. 489-494 - Ali Ozdemir, Mshabab Alrizah, Kyusun Choi:
Optimization of Comparator Selection Algorithm for TIQ Flash ADC Using Dynamic Programming Approach. 495-500 - Khanh N. Dang
TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects. 501-506 - Changlu Liu, Tianxiang Lan, Qin Li, Kaige Jia, Yidian Fan, Xing Wu, Fei Qiao, Wei Qi, Xin-Jun Liu, Huazhong Yang:
Energy-efficient Analog Processing Architecture for Direction of Arrival with Microphone Array. 507-512
Session 18: Special Session: Emerging Technologies and Architectures
- Karthikeyan Nagarajan, Sina Sayyah Ensan, Swagata Mandal, Swaroop Ghosh, Anupam Chattopadhyay:
iMACE: In-Memory Acceleration of Classic McEliece Encoder. 513-518 - Weiguang Chen, Zheng Wang, Shanliao Li, Zhibin Yu, Huijuan Li:
Accelerating Compact Convolutional Neural Networks with Multi-threaded Data Streaming. 519-522 - Renjie Yao, Yaoyao Ye, Weichen Liu
Design of a Hierarchical Clos-Benes Optical Network-on-Chip Architecture. 523-528 - Ruben Vazquez
Machine Learning-based Prediction for Phase-Based Dynamic Architectural Specialization. 529-534
Session 19: System Design and Security III
- Amin Rezaei, Jie Gu, Hi Zhou:
Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries. 535-540 - Michael Zuzak, Ankur Srivastava
Memory Locking: An Automated Approach to Processor Design Obfuscation. 541-546 - Abhishek Chakraborty, Ankur Srivastava
Hardware-Software Co-Design Based Obfuscation of Hardware Accelerators. 547-552
Session 20: Special Session: Energy-Efficient Machine Learning
- Alberto Marchisio
Deep Learning for Edge Computing: Current Trends, Cross-Layer Optimizations, and Open Research Challenges. 553-559 - Dimitrios Stathis
Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps. 560-567 - Alexandros Kouris, Stylianos I. Venieris
Towards Efficient On-Board Deployment of DNNs on Intelligent Autonomous Systems. 568-573
Session 21: Digital Circuits and FPGA Based Designs III
- Shuo Li, Xiaolin Xu, Wayne P. Burleson:
PVTMC: An All-Digital Sub-Picosecond Timing Measurement Circuit Based on Process Variations. 574-579 - Jing Zeng, Yangcan Zhou, Jun Lin, Zhongfeng Wang:
Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes. 580-585 - Surajeet Ghosh, Shaon Dasgupta, Sanchita Saha Ray:
A Comparison-free Hardware Sorting Engine. 586-591 - Joel Ortiz Sosa, Olivier Sentieys, Christian Roland:
Adaptive Transceiver for Wireless NoC to Enhance Multicast/Unicast Communication Scenarios. 592-597
Session 22: Special Session: Botnet of Things: Hardware Insecurity in the IoT Era
- Pinchen Cui, Ujjwal Guin:
Countering Botnet of Things using Blockchain-Based Authenticity Framework. 598-603 - Sreeja Chowdhury, Hao-Ting Shen, Beomsoo Park, Nima Maghari, Domenic Forte
Aging Analysis of Low Dropout Regulator for Universal Recycled IC Detection. 604-609 - Amro Awad, Suboh Suboh, Mao Ye
Persistently-Secure Processors: Challenges and Opportunities for Securing Non-Volatile Memories. 610-614
Session 23: Digital Circuits and FPGA Based Designs IV
- Fatemeh Serajeh-hassani, Mohammad Sadrosadati, Sebastian Pointner, Robert Wille, Hamid Sarbazi-Azad:
Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes. 615-620 - Süleyman Savas, Yassin Atwa, Tomas Nordström
Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit. 621-626 - Prasad Vernekar, Nithin Kumar Yernad Balachandra
Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability. 627-631
Session 24: Special Session: Secure, Smart, Connected Devices for Emergent Applications
- Yier Jin
Towards Hardware-Assisted Security for IoT Systems. 632-637 - Bryson Shannon, Spandana Etikala, Yutian Gui, Ali Shuja Siddiqui, Fareena Saqib:
Blockchain Based Distributed Key Provisioning and Secure Communication over CAN FD. 638-644
Session 25: Emerging and Post-CMOS Technologies II
- Soheil Nazar Shahsavani, Massoud Pedram:
A Hyper-Parameter Based Margin Calculation Algorithm for Single Flux Quantum Logic Cells. 645-650 - Robert Wille, Marcel Walter
Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies. 651-656
Session 26: System Design and Security IV
- Yuntao Liu
Mitigating Reverse Engineering Attacks on Deep Neural Networks. 657-662 - Shubham Rai
Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies. 663-669 - Vishalini R. Laguduva, Sheikh Ariful Islam
Machine Learning Based IoT Edge Node Security Attack and Countermeasures. 670-675
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