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ISPD 2017: Portland, OR, USA
- Mustafa Ozdal, Chris Chu:
Proceedings of the 2017 ACM on International Symposium on Physical Design, ISDP 2017, Portland, OR, USA, March 19-22, 2017. ACM 2017, ISBN 978-1-4503-4696-2
Welcome and Keynote Address
- Ian Young:
Technology Options for Beyond-CMOS. 1
Machine Learning in EDA
- Pradeep Dubey:
The Quest for The Ultimate Learning Machine. 3 - Eric S. Chung:
Deep Learning in the Enhanced Cloud. 5 - Hang Zhang
, Fengyuan Zhu, Haocheng Li
Bilinear Lithography Hotspot Detection. 7-14 - Wei-Ting Jonas Chan, Pei-Hsin Ho, Andrew B. Kahng, Prashant Saxena:
Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning. 15-21
Monday Afternoon Keynote
- Ivo Bolsens:
Pushing the boundaries of Moore's Law to transition from FPGA to All Programmable Platform. 23
Invited Poster Presentation
- Tiago Fontana, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Sheiny Almeida, Laércio Lima Pilla
How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library. 25-31 - Guilherme Flach, Mateus Fogaça
Rsyn: An Extensible Physical Synthesis Framework. 33-40
Nontraditional Physical Design Challenges
- Ramesh Karri
Research Challenges in Security-Aware Physical Design. 41 - Soroosh Khoram, Yue Zha
Challenges and Opportunities: From Near-memory Computing to In-memory Computing. 43-46 - Xifan Tang, Edouard Giacomin
Physical Design Considerations of One-level RRAM-based Routing Multiplexers. 47-54 - Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, David Z. Pan:
Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits. 55-62
Tuesday Keynote Address
- Lee-Chung Lu:
Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling Trend. 63
Clock and Timing
- Charles J. Alpert:
Modern Challenges in Constructing Clocks. 65 - Rickard Ewetz, Cheng-Kok Koh:
Clock Tree Construction based on Arrival Time Constraints. 67-74 - Gang Wu, Chris Chu:
A Fast Incremental Cycle Ratio Algorithm. 75-82 - Pei-Yu Lee, Iris Hui-Ru Jiang, Ting-You Yang:
iTimerM: Compact and Accurate Timing Macro Modeling for Efficient Hierarchical Timing Analysis. 83-89
Routability Considerations
- Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin
DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment. 91-98 - Pascal Cremer, Stefan Hougardy, Jan Schneider, Jannik Silvanus:
Automatic Cell Layout in the 7nm Era. 99-106 - Daohang Shi, Azadeh Davoodi:
Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells. 107-112
Commemoration for Professor Satoshi Goto
- Yuichi Nakamura:
The Spirit of in-house CAD Achieved by the Legend of Master "Prof. Goto" and his Apprentices. 113-114 - Yao-Wen Chang:
Generalized Force Directed Relaxation with Optimal Regions and Its Applications to Circuit Placement. 115-120 - Jinjia Zhou
100x Evolution of Video Codec Chips. 121-122 - Ilgweon Kang, Chung-Kuan Cheng:
Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond. 123-128 - Satoshi Goto:
Past, Present and Future of the Research. 129-130
Optimization and Placement
- Pei-Hsin Ho:
Interesting Problems in Physical Synthesis. 131 - Yixiao Ding, Chris Chu, Wai-Kei Mak:
Pin Accessibility-Driven Detailed Placement Refinement. 133-140 - Nima Karimpour Darav, Ismail S. Bustany, Andrew A. Kennings, Laleh Behjat
A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement. 141-148
FPGA CAD and Contest
- Mahesh A. Iyer:
CAD Opportunities with Hyper-Pipelining. 149 - Shounak Dhar, Mahesh A. Iyer
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs. 151-157 - Stephen Yang, Chandra Mulpuri, Sainath Reddy, Meghraj Kalase, Srinivasan Dasasathyan, Mehrdad E. Dehkordi, Marvin Tom, Rajat Aggarwal:
Clock-Aware FPGA Placement Contest. 159-164
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