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26th HPCA 2020: San Diego, CA, USA
- IEEE International Symposium on High Performance Computer Architecture, HPCA 2020, San Diego, CA, USA, February 22-26, 2020. IEEE 2020, ISBN 978-1-7281-6149-5
- Mohsen Imani, Mohammad Samragh Razlighi, Yeseong Kim, Saransh Gupta, Farinaz Koushanfar
, Tajana Rosing:
Deep Learning Acceleration with Neuron-to-Memory Transformation. 1-14 - Mingyu Yan, Lei Deng
HyGCN: A GCN Accelerator with Hybrid Architecture. 15-29 - Ismail Akturk, Ulya R. Karpuzcu:
ACR: Amnesic Checkpointing and Recovery. 30-43 - Jingwen Leng, Alper Buyuktosunoglu, Ramon Bertran
Asymmetric Resilience: Exploiting Task-Level Idempotency for Transient Error Recovery in Accelerator-Based Systems. 44-57 - Eric Qin, Ananda Samajdar, Hyoukjun Kwon
SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training. 58-70 - Nader Sehatbakhsh
EMSim: A Microarchitecture-Level Simulation Tool for Modeling Electromagnetic Side-Channel Signals. 71-85 - Elaheh Sadredini
Impala: Algorithm/Architecture Co-Design for In-Memory Multi-Stride Pattern Matching. 86-98 - Ting-Ru Lin, Drew Penney, Massoud Pedram, Lizhong Chen:
A Deep Reinforcement Learning Framework for Architectural Exploration: A Routerless NoC Case Study. 99-110 - Hamza Omar, Omer Khan:
IRONHIDE: A Secure Multicore that Efficiently Mitigates Microarchitecture State Attacks for Interactive Applications. 111-122 - Nader Sehatbakhsh
A New Side-Channel Vulnerability on Modern Computers by Exploiting Electromagnetic Emanations from the Power Management Unit. 123-138 - Wenjie Xiong
Leaking Information Through Cache LRU States. 139-152 - Mohammad Reza Jokar, Junyi Qiu, Frederic T. Chong
Baldur: A Power-Efficient and Scalable Network Using All-Optical Switches. 153-166 - Rajiv Nishtala, Vinicius Petrucci, Paul M. Carpenter, Magnus Själander:
Twig: Multi-Agent Task Management for Colocated Latency-Critical Cloud Services. 167-179 - Reid Pinkham, Shuqing Zeng, Zhengya Zhang
QuickNN: Memory and Performance Optimization of k-d Tree Based Nearest Neighbor Search for 3D Point Clouds. 180-192 - Tirthak Patel
CLITE: Efficient and QoS-Aware Co-Location of Multiple Latency-Critical Jobs for Warehouse Scale Computers. 193-206 - Amirhossein Mirhosseini, Brendan L. West, Geoffrey W. Blake, Thomas F. Wenisch:
Q-Zilla: A Scheduling Framework and Core Microarchitecture for Tail-Tolerant Microservices. 207-219 - Yujeong Choi, Minsoo Rhu:
PREMA: A Predictive Multi-Task Scheduling Algorithm For Preemptible Neural Processing Units. 220-233 - Priyank Faldu
Domain-Specialized Cache Management for Graph Analytics. 234-248 - Bahar Asgari
ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator. 249-260 - Zhekai Zhang, Hanrui Wang, Song Han, William J. Dally:
SpArch: Efficient Architecture for Sparse Matrix Multiplication. 261-274 - Farzaneh Zokaee, Lei Jiang:
Mitigating Voltage Drop in Resistive Memories by Dynamic RESET Voltage Regulation and Partition RESET. 275-286 - Jie Zhang, Gyuyoung Park, David Donofrio, John Shalf
DRAM-Less: Hardware Acceleration of Data Processing with New Memory. 287-302 - Xin Xin, Youtao Zhang, Jun Yang:
ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM. 303-314 - Keni Qiu, Nicholas Jao, Mengying Zhao, Cyan Subhra Mishra
ResiRCA: A Resilient Energy Harvesting ReRAM Crossbar-Based Accelerator for Intelligent Embedded Processors. 315-327 - Tae Jun Ham, Sungjun Jung, Seonghak Kim, Young H. Oh, Yeonhong Park, Yoonho Song
A3: Accelerating Attention Mechanisms in Neural Networks with Approximation. 328-341 - Linghao Song
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators. 342-355 - Donald Kline Jr., Jiangwei Zhang, Rami G. Melhem, Alex K. Jones
FLOWER and FaME: A Low Overhead Bit-Level Fault-map and Fault-Tolerance Approach for Deeply Scaled Memories. 356-368 - Yuezhi Che, Rujia Wang:
Multi-Range Supported Oblivious RAM for Efficient Block Data Retrieval. 369-382 - Ipoom Jeong
CASINO Core Microarchitecture: Generating Out-of-Order Schedules Using Cascaded In-Order Scheduling Windows. 383-396 - Ajeya Naithani
Precise Runahead Execution. 397-410 - Liang Zhu, Chao Chen, Zihao Su, Weiguang Chen, Tao Li, Zhibin Yu:
BBS: Micro-Architecture Benchmarking Blockchain Systems through Machine Learning and Fuzzy Set. 411-423 - Mehdi Alipour, Stefanos Kaxiras, David Black-Schaffer, Rakesh Kumar:
Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors. 424-434 - Yunfan Li, Lizhong Chen:
EquiNox: Equivalent NoC Injection Routers for Silicon Interposer-Based Throughput Processors. 435-446 - Mayank Parasar, Hossein Farrokhbakht, Natalie D. Enright Jerger
DRAIN: Deadlock Removal for Arbitrary Irregular Networks. 447-460 - Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, Mark Hempstead:
SnackNoC: Processing in the Communication Layer. 461-473 - Kyle Shiflett, Dylan Wright, Avinash Karanth
PIXEL: Photonic Neural Network Accelerator. 474-487 - Udit Gupta
The Architectural Implications of Facebook's DNN-Based Personalized Recommendation. 488-501 - Changmin Lee, Wonjae Shin, Dae Jeong Kim, Yongjun Yu, Sung-Joon Kim, Taekyeong Ko, Deokho Seo, Jongmin Park, Kwanghee Lee, Seongho Choi, Namhyung Kim, Vishak G, Arun George, Vishwas V, Donghun Lee, Kang-Woo Choi, Changbin Song, Dohan Kim, Insu Choi, Ilgyu Jung, Yong Ho Song, Jinman Han:
NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces. 502-514 - Daniel Richins, Dharmisha Doshi, Matthew Blackmore, Aswathy Thulaseedharan Nair, Neha Pathapati, Ankit Patel, Brainard Daguman, Daniel Dobrijalowski, Ramesh Illikkal, Kevin Long, David Zimmerman, Vijay Janapa Reddi:
Missing the Forest for the Trees: End-to-End AI Application Performance in Edge Data Centers. 515-528 - Xiaoming Chen, Yinhe Han, Yu Wang:
Communication Lower Bound in Convolution Accelerators. 529-541 - Xingyao Zhang
Enabling Highly Efficient Capsule Networks Processing Through A PIM-Based Architecture Design. 542-555 - Marzieh Lenjani, Patricia Gonzalez-Guerrero, Elaheh Sadredini
Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators. 556-569 - Gurunath Kadam
BCoal: Bucketing-Based Memory Coalescing for Efficient and Secure GPUs. 570-581 - Xiaowei Ren, Daniel Lustig, Evgeny Bolotin, Aamer Jaleel, Oreste Villa, David W. Nellans:
HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems. 582-595 - Trinayan Baruah, Yifan Sun
Griffin: Hardware-Software Support for Efficient Page Migration in Multi-GPU Systems. 596-609 - Jianbo Dong, Zheng Cao
EFLOPS: Algorithm and System Co-Design for a High Performance Distributed Training Platform. 610-622 - Jawad Haj-Yahya, Yanos Sazeides, Mohammed Alser, Efraim Rotem, Onur Mutlu:
Techniques for Reducing the Connected-Standby Energy Consumption of Mobile Devices. 623-636 - Jieming Yin, Subhash Sethumurugan, Yasuko Eckert, Chintan Patel, Alan Smith, Eric Morton, Mark Oskin, Natalie D. Enright Jerger
Experiences with ML-Driven Design: A NoC Case Study. 637-648 - Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso
Hybrid2: Combining Caching and Migration in Hybrid Memory Systems. 649-662 - Seikwon Kim, Wonsang Kwak, Changdae Kim, Daehyeon Baek
Charge-Aware DRAM Refresh Reduction with Value Transformation. 663-676 - Jian Chen, Ying Zhang, Xiaowei Jiang, Li Zhao, Zheng Cao
DWT: Decoupled Workload Tracing for Data Centers. 677-688 - Nitish Kumar Srivastava, Hanchen Jin, Shaden Smith, Hongbo Rong, David H. Albonesi, Zhiru Zhang
Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations. 689-702 - Jian Weng, Sihao Liu
A Hybrid Systolic-Dataflow Architecture for Inductive Matrix Algorithms. 703-716 - Adrián Barredo
Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions. 717-728
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