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HOST 2016: McLean, VA, USA
- William H. Robinson, Swarup Bhunia, Ryan Kastner:
2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016, McLean, VA, USA, May 3-5, 2016. IEEE Computer Society 2016, ISBN 978-1-4673-8826-9 - Ye Zhang, Farinaz Koushanfar
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Robust privacy-preserving fingerprint authentication. 1-6 - Kun Yang, Domenic Forte
UCR: An unclonable chipless RFID tag. 7-12 - Rui Liu, Huaqiang Wu, Yachun Pang, He Qian, Shimeng Yu
A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation. 13-18 - Arunkumar Vijayakumar, Vinay C. Patil, Charles B. Prado, Sandip Kundu:
Machine learning resistant strong PUF: Possible or a pipe dream? 19-24 - Wei-Che Wang, Yair Yona, Suhas N. Diggavi, Puneet Gupta
LEDPUF: Stability-guaranteed physical unclonable functions through locally enhanced defectivity. 25-30 - Sikhar Patranabis, Debapriya Basu Roy, Yash Shrivastava, Debdeep Mukhopadhyay, Santosh Ghosh:
Parsimonious design strategy for linear layers with high diffusion in block ciphers. 31-36 - Vladimir Rozic, Bohan Yang, Wim Dehaene, Ingrid Verbauwhede
Iterating Von Neumann's post-processing under hardware constraints. 37-42 - Arun K. Kanuparthi, Jeyavijayan Rajendran, Ramesh Karri
Controlling your control flow graph. 43-48 - Michael Tempelmeier
An area-optimized serial implementation of ICEPOLE authenticated encryption schemes. 49-54 - Subhadeep Banik
Round gating for low energy block ciphers. 55-60 - Jeffrey Todd McDonald, Yong C. Kim, Todd R. Andel, Miles A. Forbes, James McVicar:
Functional polymorphism for intellectual property protection. 61-66 - Ehsan Aerabi, A. Elhadi Amirouche, Houda Ferradi, Rémi Géraud
The Conjoined Microprocessor. 67-70 - Subhadeep Banik
Low-area hardware implementations of CLOC, SILC and AES-OTR. 71-74 - Jacob Couch
Functional block identification in circuit design recovery. 75-78 - Fatemeh Tehranipoor, Wei Yan, John A. Chandy
Robust hardware true random number generators using DRAM remanence effects. 79-84 - Rodrigo Branco, Shay Gueron
Blinded random corruption attacks. 85-90 - Jonathan Graf:
Trust games: How game theory can guide the development of hardware Trojan detection methods. 91-96 - Henrique Kawakami, David Ott, Hao Chi Wong, Ricardo Dahab
ACBuilder: A tool for hardware architecture security evaluation. 97-102 - Alexander Wild, Georg T. Becker, Tim Güneysu
On the problems of realizing reliable and efficient ring oscillator PUFs on FPGAs. 103-108 - Chris Bradfield, Cynthia Sturton:
Model checking to find vulnerabilities in an instruction set architecture. 109-113 - Ofir Shwartz, Yitzhak Birk
SDSM: Fast and scalable security support for directory-based distributed shared memory. 114-119 - Amey M. Kulkarni, Youngok K. Pino, Tinoosh Mohsenin:
Adaptive real-time Trojan detection framework through machine learning. 120-123 - Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra
Scalable SoC trust verification using integrated theorem proving and model checking. 124-129 - Johannes Bauer, Sebastian Schinzel, Felix C. Freiling, Andreas Dewald:
Information leakage behind the curtain: Abusing anti-EMI features for covert communication. 130-134 - Maxime Lecomte, Jacques J. A. Fournier, Philippe Maurine:
Granularity and detection capability of an adaptive embedded Hardware Trojan detection system. 135-138 - Ryan L. Helinski, Edward I. Cole, Gideon Robertson, Jonathan Woodbridge, Lyndon G. Pierson:
Electronic forensic techniques for manufacturer attribution. 139-144 - Arvind Singh, Monodeep Kar, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Integrated all-digital low-dropout regulator as a countermeasure to power attack in encryption engines. 145-148 - Azalia Mirhoseini, Ahmad-Reza Sadeghi, Farinaz Koushanfar
CryptoML: Secure outsourcing of big data machine learning applications. 149-154 - Qihang Shi, Navid Asadizanjani, Domenic Forte
A layout-driven framework to assess vulnerability of ICs to microprobing attacks. 155-160 - Rui Qiao, Mark Seaborn:
A new approach for rowhammer attacks. 161-166 - Liwei Zhou, Yiorgos Makris
Hardware-based workload forensics: Process reconstruction via TLB monitoring. 167-172 - David Whelihan, Kate Thurmer, Michael Vai:
A key-centric processor architecture for secure computing. 173-178 - Brent Sherman, David Wheeler:
Hardware security risk assessment: A case study. 179-184 - Fathi Amsaad, Atul Prasad, Chayanika Roychaudhuri, Mohammed Y. Niamat:
A novel security technique to generate truly random and highly reliable reconfigurable ROPUF-based cryptographic keys. 185-190 - Zimu Guo, Md. Tauhidur Rahman
A zero-cost approach to detect recycled SoC chips using embedded SRAM. 191-196 - Bradley D. Hopkins
Redirecting DRAM memory pages: Examining the threat of system memory Hardware Trojans. 197-202 - Falk Schellenberg
Large laser spots and fault sensitivity analysis. 203-208 - Jakub Breier
The other side of the coin: Analyzing software encoding schemes against fault injection attacks. 209-216 - Peter Samarin, Kerstin Lemke-Rust, Christof Paar:
IP core protection using voltage-controlled side-channel receivers. 217-222 - Luis Ramirez Rivera, Xiaofang Wang, Danai Chasaki:
A separation and protection scheme for on-chip memory blocks in FPGAs. 223-228 - Burak Erbagci, Cagri Erbagci, Nail Etkin Can Akkaya, Ken Mai:
A secure camouflaged threshold voltage defined logic family. 229-235 - Muhammad Yasin
SARLock: SAT attack resistant logic locking. 236-241 - Elif Ozgen, Louiza Papachristodoulou, Lejla Batina:
Template attacks using classification algorithms. 242-247 - M. Sadegh Riazi, Neeraj K. R. Dantu, L. N. Vinay Gattu, Farinaz Koushanfar
GenMatch: Secure DNA compatibility testing. 248-253
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