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FPT 2007: Kitakyushu, Japan
- Hideharu Amano, Andy Ye, Takeshi Ikenaga:
2007 International Conference on Field-Programmable Technology, ICFPT 2007, Kitakyushu, Japan, December 12-14, 2007. IEEE 2007, ISBN 1-4244-1472-5
Keynotes
- Sinan Kaptanoglu:
Power and the Future FPGA Architectures. - Kei Hiraki:
GRAPE-DR Project: a combination of peta-scale computing and high-speed networking.
Tools I
- Scott Y. L. Chin, Steven J. E. Wilton:
Memory Footprint Reduction for FPGA Routing Algorithms. 1-8 - Gopalakrishnan Seetharaman, Balasubramanian Venkataramani:
SOC implementation of wave-pipelined circuits. 9-16 - Justin S. J. Wong
, N. Pete Sedcole, Peter Y. K. Cheung:
Self-characterization of Combinatorial Circuit Delays in FPGAs. 17-23
Applications I
- Cameron D. Patterson, Brian S. Martin, Steven W. Ellingson, John H. Simonetti, Sean E. Cutchin:
FPGA Cluster Computing in the ETA Radio Telescope. 25-32 - Ning-Yi Xu, Xiongfei Cai, Rui Gao, Lei Zhang, Feng-Hsiung Hsu:
FPGA-based Accelerator Design for RankBoost in Web Search Engines. 33-40 - Xin Xie, John A. Williams
Asymmetric Multi-Processor Architecture for Reconfigurable System-on-Chip and Operating System Abstractions. 41-48 - Sailesh Pati, Ramanathan Narayanan, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno:
Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction. 49-56
Architecture
- Peter Jamieson, Jonathan Rose:
Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters. 57-64 - Jason V. Paul, Samuel J. Stone, Yong C. Kim, Robert W. Bennington:
A Method and FPGA Architecture for Real-Time Polymorphic Reconfiguration. 65-71 - Jonathan Evans, Kyle Rupnow
Reconfigurable Functional Units for Scientific Superscalar Processors. 73-80 - Ruchika Verma
A Coarse Grained Reconfigurable Architecture for Variable Block Size Motion Estimation. 81-88
Tools II
- William George Osborne, José Gabriel F. Coutinho, Ray C. C. Cheung
Instrumented Multi-Stage Word-Length Optimization. 89-96 - David B. Thomas, Wayne Luk:
A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations. 97-104 - Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction. 105-112 - Jacob A. Bower, Wei Ning Cho, Wayne Luk:
Unifying FPGA Hardware Development. 113-120
Applications II
- Tran Ngoc Thinh, Surin Kittitornkun, Shigenori Tomiyama:
Applying Cuckoo Hashing for FPGA-based Pattern Matching in NIDS/NIPS. 121-128 - Marco Aurelio Nuño-Maganda
High Performance Hardware Implementation of SpikeProp Learning: Potential and Tradeoffs. 129-136 - Fabio Augusto Cappabianco, Guido Araujo, Alexandre X. Falcão:
The Image Forest Transform Architecture. 137-144 - Sandeep K. Venishetti, Ali Akoglu
A Highly Parallel FPGA based IEEE-754 Compliant Double-Precision Binary Floating-Point Multiplication Algorithm. 145-152
Memory & IP Protection
- Weisheng Zhao, Eric Belhaire, Bernard Dieny, Guillaume Prenat, Claude Chappert:
TAS-MRAM based Non-volatile FPGA logic circuit. 153-160 - Dirk Koch, Christian Beckhoff, Jürgen Teich:
Bitstream Decompression for High Speed FPGA Configuration from Slow Memories. 161-168 - Tim Güneysu
Dynamic Intellectual Property Protection for Reconfigurable Devices. 169-176
Applications III
- Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch, Shuo Yang, Tiago Perez, Zhen'An Liu:
Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics. 177-183 - Gang Zhou, Harald Michalik, László Hinsenkamp:
Efficient and High-Throughput Implementations of AES-GCM on FPGAs. 185-192 - Masato Yoshimi, Yuri Nishikawa
A Framework for Implementing a Network-Based Stochastic Biochemical Simulator on an FPGA. 193-200 - Shingo Kawada, Tsutomu Maruyama:
An Approach for Applying Large Filters on Large Images using FPGA. 201-208
Tools III
- Krzysztof Kosciuszkiewicz, Fearghal Morgan, Krzysztof Kepa
Run-Time Management of Reconfigurable Hardware Tasks Using Embedded Linux. 209-215 - Tsutomu Sasao, Hiroki Nakahara:
Implementations of Reconfigurable Logic Arrays on FPGAs. 217-223 - Audip Pandit, Ali Akoglu
Net Length based Routability Driven Packing. 225-232
Poster Session
- Kentaro Sano, Oliver Pell, Wayne Luk, Satoru Yamamoto:
FPGA-based Streaming Computation for Lattice Boltzmann Method. 233-236 - Kai-Jung Shih
Reconfigurable Hardware Module Sequencer - A Tradeoff Between Networked and Data Flow Architectures. 237-240 - Yoshiaki Satou, Motoki Amagasaki, Hiroshi Miura, Kazunori Matsuyama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi:
An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell Architecture. 241-244 - Tim Todman, Haofan Fu, Oskar Mencer, Wayne Luk:
Improving Bounds for FPGA Logic Minimization. 245-248 - Georgi Kuzmanov, Wouter M. van Oijen:
Floating-Point Matrix Multiplication in a Polymorphic Processor. 249-252 - Yohei Hori
A Secure Digital Content Delivery System Based on Partially Reconfigurable Hardware. 253-256 - Esam El-Araby
Productivity of High-Level Languages on Reconfigurable Computers: An HPC Perspective. 257-260 - Yoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama:
A Systolic Algorithm for the Quadratic Assignment Problem and its FPGA Implementation. 261-264 - Daisaku Seto, Minoru Watanabe:
Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture. 265-268 - Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez:
Efficient Mesh of Tree Interconnect for FPGA Architecture. 269-272 - Satoshi Tsutsumi, Vasutan Tunbunheng, Yohei Hasegawa, Adepu Parimala, Takuro Nakamura, Takashi Nishimura, Hideharu Amano:
Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays. 273-276 - David P. Coggins, David W. P. Thomas, Barrie Hayes-Gill, Yiqun Zhu:
An FPGA Based Travelling-Wave Fault Location System. 277-280 - Xianyang Jiang, Xiaomin Li, Yue Tian, Kai Wang:
NICFlex: A Functional Verification Accelerator for An RTL NIC Design. 281-284 - Masakazu Hioki
A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip. 285-288 - Yi-Ru He, Wai-Kei Mak:
Optimal Buffering of FPGA Interconnect for Expected Delay Optimization. 289-292 - Yusuke Yachide, Makoto Ikeda, Kunihiro Asada:
FPGA-Based 3-D engine for high-speed 3-D measurement based on light-section method. 293-296 - Mao Nakajima, Minoru Watanabe:
A 62.5 ns holographic reconfiguration of an optically differential reconfigurable gate array. 297-300 - Zubair Nawaz, Ozana Silvia Dragomir, Thomas Marconi, Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis:
Recursive Variable Expansion: A Loop Transformation for Reconfigurable Systems. 301-304 - Naoto Miyamoto, Masahiko Shimakage, Tatsuo Morimoto, Kazuya Kadota, Shigetoshi Sugawa, Tadahiro Ohmi:
A Rapid Prototyping of Real-Time Pattern Generator for Step-and-Scan Lithography Using Digital Micromirror Device. 305-308 - Ryan B. Proudfoot, Kenneth B. Kent
High Performance Software-Hardware Network Intrusion Detection System. 309-312 - Heiko Hinkelmann, Peter Zipf
A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks. 313-316 - Shinsuke Nino, Takayuki Mori, YoungHun Ko, Yuichiro Shibata, Kiyoshi Oguri:
FPGA Implementation of a Statically Reconfigurable Java Environment for Embedded Systems. 317-320 - Nao Iwata, Shingo Kagami, Koichi Hashimoto
A Dynamically Reconfigurable Architecture Combining Pixel-Level SIMD and Operation-Pipeline Modes for High Frame Rate Visual Processing. 321-324 - Masahiro Konda, Takahiro Nakayama, Naoto Miyamoto, Tadahiro Ohmi:
A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture Compression. 325-328 - Takashi Saegusa, Tsutomu Maruyama:
Real-Time Segmentation of Color Images based on the K-means Clustering on FPGA. 329-332 - Miaoqing Huang, Iván González
A Portable Memory Access Framework on Reconfigurable Computers. 333-336 - Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis:
The Spiral Search: A Linear Complexity Algorithm for the Generation of Convex MIMO Instruction-Set Extensions. 337-340 - Jason Yu, Guy Lemieux:
A Case for Soft Vector Processors in FPGAs. 341-344 - Takahito Nakajima, Shigeru Namiki, Shuhei Kinoshita, Naohiko Shimizu:
A Portable Co-Verification System Which Generates Testbench Automatically. 345-348 - William Kamp
Multiply Accumulate Unit Optimised for Fast Dot-Product Evaluation. 349-352 - Jenny Yi-Chun Kuo, Hossam A. ElGindy, Anderson Kuei-An Ku:
A Novel Network Architecture Support for Fast Reconfiguration. 353-356 - Vu Manh Tuan, Hideharu Amano:
A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors. 357-360 - Akira Yamawaki, Masahiko Iwane:
A Programmable Load/Store Unit on C-based Hardware Design for FPGA. 361-364 - Dimitrios Meintanis, Ioannis Papaefstathiou
An efficient FPGA-based implementation of Pollard's (ρ - 1) factorization algorithm. 365-368 - Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri
A Novel Asynchronous e-FPGA Architecture for Security Applications. 369-372 - James Dykes, Paulman Chan, Glenn H. Chapman, Lesley Shannon:
A Multiprocessor System-on-Chip Implementation of a Laser-based Transparency Meter on an FPGA. 373-376 - Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel:
Compound Uniform Random Number Generators with On-Chhip Correlation and Distribution Measurements. 377-380 - Thomas Schweizer, Tobias Oppold, Julio A. de Oliveira Filho, Sven Eisenhardt, Kai Blocher, Wolfgang Rosenstiel:
Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures. 381-384
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