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17th FMCAD 2017: Vienna, Austria
- Daryl Stewart, Georg Weissenbacher:
2017 Formal Methods in Computer Aided Design, FMCAD 2017, Vienna, Austria, October 2-6, 2017. IEEE 2017, ISBN 978-0-9835678-7-5
Invited Papers
- Shin'ichiro Matsuo:
How formal analysis and verification add security to blockchain-based systems. 1-4 - Cas Cremers:
Symbolic security analysis using the Tamarin prover. 5 - Jade Alglave:
Coalition, intrigue, ambush, destruction and pride: Herding cats can be challenging. 6 - Byron Cook:
Automated formal reasoning about AWS systems. 7 - Wilfried Steiner:
Formal methods in industrial dependable systems design - The TTTech example. 8 - Armin Biere
, Tom van Dijk
Hardware model checking competition 2017. 9 - Keijo Heljanko
The FMCAD 2017 graduate student forum. 10
Arithmetic
- M. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz:
goSAT: Floating-point satisfiability as global optimization. 11-14 - Anastasiia Izycheva, Eva Darulova
On sound relative error bounds for floating-point arithmetic. 15-22 - Daniela Ritirc
Column-wise verification of multipliers using computer algebra. 23-30
Solving
- Elaheh Ghassabani, Michael W. Whalen, Andrew Gacek:
Efficient generation of all minimal inductive validity cores. 31-38 - Leonardo Alt, Antti Eero Johannes Hyvärinen, Sepideh Asadi
Duality-based interpolation for quantifier-free equalities and uninterpreted functions. 39-46 - Yakir Vizel, Alexander Nadel
Solving linear arithmetic with SAT-based model checking. 47-54 - Murphy Berzish, Vijay Ganesh
Z3str3: A string solver with theory-aware heuristics. 55-59
Concurrency and Distributed Systems
- Christopher J. Banks
Verification of a lazy cache coherence protocol against a weak memory model. 60-67 - Zeinab Ganjei, Ahmed Rezine, Petru Eles, Zebo Peng:
Safety verification of phaser programs. 68-75 - Yu-Fang Chen, Chih-Duo Hong
Learning to prove safety over parameterised concurrent systems. 76-83 - Rashmi Mudduluru, Pantazis Deligiannis
Lasso detection using partial-state caching. 84-91
Probabilistic Systems
- Matthew S. Bauer, Umang Mathur
Exact quantitative probabilistic model checking through rational search. 92-99 - Grigory Fedyukovich
Sampling invariants from frequency distributions. 100-107
BDDs
- Tom van Dijk
Tagged BDDs: Combining reduction rules from different decision diagram types. 108-115 - Klaus Havelund, Doron Peled, Dogan Ulus
First order temporal logic monitoring with BDDs. 116-123 - Lucas M. Tabajara, Moshe Y. Vardi:
Factored boolean functional synthesis. 124-131
IC3
- Yen-Sheng Ho, Alan Mishchenko, Robert K. Brayton:
Property directed reachability with word-level abstraction. 132-139 - Ryan Berryhill, Alexander Ivrii, Neil Veira, Andreas G. Veneris:
Learning support sets in IC3 and Quip: The good, the bad, and the ugly. 140-147 - Arie Gurfinkel
K-induction without unrolling. 148-155 - Matteo Marescotti, Arie Gurfinkel
Designing parallel PDR. 156-163 - Rohit Dureja
FuseIC3: An algorithm for checking large design spaces. 164-171 - Sylvain Conchon, Amit Goel, Sava Krstic, Rupak Majumdar, Mattias Roux:
FAR-Cubicle - A new reachability algorithm for Cubicle. 172-175 - Tamás Tóth
Theta: A framework for abstraction refinement-based model checking. 176-179
Hybrid Systems
- Kyungmin Bae, Sicun Gao:
Modular SMT-based analysis of nonlinear hybrid systems. 180-187 - Alessandro Cimatti, Sergio Mover, Mirko Sessa
SMT-based analysis of switching multi-domain linear Kirchhoff networks. 188-195
Applications
- Hans-Peter Deifel, Merlin Göttlinger
Automatic verification of application-tailored OSEK kernels. 196-203 - Freek Verbeek, Nike van Vugt:
Estimating worst-case latency of on-chip interconnects with formal simulation. 204-211 - Arnaud Sangnier
Parameterized verification of algorithms for oblivious robots on a ring. 212-219 - William T. Hallahan
Automated repair by example for firewalls. 220-229
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