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DFT 2016: Storrs, CT, USA
- 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016, Storrs, CT, USA, September 19-20, 2016. IEEE Computer Society 2016, ISBN 978-1-5090-3623-3
- Omer Khan, Maria K. Michael, Antonio Miele
, Qiaoyan Yu:
Foreword. iii
Session 1: Aging
- Hardeep Chahal
BTI aware thermal management for reliable DVFS designs. 1-6 - Naghmeh Karimi, Ke Huang:
Prognosis of NBTI aging using a machine learning scheme. 7-10 - Glenn H. Chapman, Rahul Thomas, Rohan Thomas, Israel Koren, Zahava Koren:
Experimental study and analysis of soft and permanent errors in digital cameras. 11-14
Session 2: Fault Tolerance in Latches & Approximate Computing
- Adam Watkins, Spyros Tragoudas:
A Highly Robust Double Node Upset Tolerant latch. 15-20 - Alexander Schöll, Claus Braun, Hans-Joachim Wunderlich:
Applying efficient fault tolerance to enable the preconditioned conjugate gradient solver on approximate computing hardware. 21-26 - Hiroki Ueno, Kazuteru Namba:
Construction of a soft error (SEU) hardened Latch with high critical charge. 27-30 - Ke Chen, Fabrizio Lombardi, Jie Han:
Design and analysis of an approximate 2D convolver. 31-34
Session 3: System-level Approaches
- Cristiana Bolchini, Matteo Carminati, Tulika Mitra
Combined on-line lifetime-energy optimization for asymmetric multicores. 35-40 - Chao Chen, Jacopo Panerati
Effects of online fault detection mechanisms on Probabilistic Timing Analysis. 41-46 - Mojing Liu, Brett H. Meyer:
Bounding error detection latency in safety critical systems with enhanced Execution Fingerprinting. 47-52 - Hananeh Aliee, Stefan Vitzethum, Michael Glaß
Guiding Genetic Algorithms using importance measures for reliable design of embedded systems. 53-56
Session 4: Special Session on Fault-tolerant Realtime Systems
- Zaid Al-bayati, Brett H. Meyer, Haibo Zeng:
Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures. 57-62 - Siva Satyendra Sahoo
Cross-layer fault-tolerant design of real-time systems. 63-68 - Luca Santinelli, Zhishan Guo
Fault-aware sensitivity analysis for probabilistic real-time systems. 69-74
Session 5: FPGA & CMOS Technologies
- Marcos T. Leipnitz, Eduardo Nunes de Souza, Gabriel L. Nazar:
Low cost resilient regular expression matching on FPGAs. 75-80 - Juexiao Su, Ju-Yueh Lee, Chang Wu, Lei He:
In-place LUT polarity inVersion to mitigate soft errors for FPGAs. 81-86 - Hassan Ebrahimi, Alireza Rohani, Hans G. Kerkhoff:
Detecting intermittent resistive faults in digital CMOS circuits. 87-90 - Xabier Iturbe
Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU. 91-96
Session 6: Architecture-level Techniques
- Ahmed Ibrahim
Efficient utilization of hierarchical iJTAG networks for interrupts management. 97-102 - Abdulaziz Eker, Oguz Ergin
Error recovery through partial value similarity. 103-106 - Riccardo Cantoro
In-field functional test programs development flow for embedded FPUs. 107-110 - Filippo Giuliani, Marco Ottavi
Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams. 111-114
Session 7: Fault Tolerance in NoC & SoC
- Ronak Salamat, Masoumeh Ebrahimi, Nader Bagherzadeh
CoBRA: Low cost compensation of TSV failures in 3D-NoC. 115-120 - Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis:
A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs. 121-126 - Juman Alshraiedeh, Avinash Kodi:
An adaptive routing algorithm to improve lifetime reliability in NoCs architecture. 127-130 - Gianluca Furano
A novel method for SEE validation of complex SoCs using Low-Energy Proton beams. 131-134
Session 8: Special Session on the use of VLSI Techniques for Securing ICs against Attacks
- Xiaolin Xu, Daniel E. Holcomb:
Reliable PUF design using failure patterns from time-controlled power gating. 135-140 - Anirudh Iyengar, Swaroop Ghosh, Nitin Rathi, Helia Naeimi:
Side channel attacks on STTRAM and low-overhead countermeasures. 141-146 - Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu:
On meta-obfuscation of physical layouts to conceal design characteristics. 147-152 - Xiaotong Cui, Kaijie Wu, Siddharth Garg, Ramesh Karri
Can flexible, domain specific programmable logic prevent IP theft? 153-157
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