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4th IEEE Symposium on Computer Arithmetic 1978: Santa Monica, CA, USA
- 4th IEEE Symposium on Computer Arithmetic, ARITH 1978, Santa Monica, CA, USA, October 25-27, 1978. IEEE Computer Society 1978
- David W. Matula:
Basic digit sets for radix representation of the integers. 1-9 - R. Nigel Horspool, Eric C. R. Hehner:
Exact arithmetic using a variable-length P-ADIC representation. 10-14 - Kai Hwang, T. P. Chang:
An interleaved rational/radix arithmetic system for high-precision computations. 15-24 - Israel Koren, Yoram Maliniak:
A unified approach to a class of number systems. 25-28 - David W. Matula, Peter Kornerup:
A feasibility analysis of binary fixed-slash and floating-slash number systems. 29-38 - Peter Kornerup, David W. Matula:
A feasibility analysis of fixed-slash rational arithmetic. 39-47 - Arunas G. Slekys, Algirdas Avizienis:
A modified bi-imaginary number system. 48-55 - Lawrence A. Liddiard:
Required scientific floating point arithmetic. 56-62 - Thomas E. Hull:
Desirable floating-point arithmetic and elementary functions for numerical computation. 63-69 - Krzysztof S. Frankowski:
A realistic model for error estimates in the evaluation of elementary functions. 70-74 - Eric K. Reuter, John P. Jeter, J. Wayne Anderson, Bruce D. Shriver:
Some experiments using interval arithmetic. 75-80 - E. V. Kriphnamurthy, H. Venkateswaran:
Multivariable polynomial processing - Applications to interpolation. 81-87 - Dharma P. Agrawal:
On arithmetic inter-relationships and hardware interchangeabiltty of negabinary and binary systems. 88-96 - Oscar N. Garcia, Harvey Glass, Stanley C. Haimes:
An approximate and empirical study of the distribution of adder inputs and maximum carry length propagation. 97-103 - Dharma P. Agrawal, T. R. N. Rao:
On modulo (2n+1) arithmetic logic. 104-108 - Catherine Y. Chow, James E. Robertson:
Logical design of a redundant binary adder. 109-115 - Arnold Weinberger:
Parallel adders using standard plas. 116-124 - Daniel E. Atkins, Shauchi Ong:
A comparison of two approaches to multi-operand binary addition. 125-139 - Luigi Dadda:
Multiple addition of binary serial numbers. 140-148 - Raymond S. Lim:
High-speed multiplication and multiple summand addition. 149-153 - Kwang G. Tan:
The theory and implementations of high-radix division. 154-163 - Kishor S. Trivedi, Joseph G. Rusnak:
Higher radix on-line division. 164-174 - Celia Wrathall, Tien Chi Chen:
Convergence guarantee and improvements for a fast hardware exponential and logarithm evaluation scheme. 175-182 - Milos D. Ercegovac:
An on-line square rooting algorithm. 183-189 - Milos D. Ercegovac, Melvin M. Takata:
An arithmetic module for efficient evaluation of functions. 190-199 - Fabio Alberto Schreiber, R. Stefanelli:
Two methods for fast integer binary-BCD conversion. 200-207 - Antonín Svoboda:
Arithmetic circuit fault detection by modular encoding. 208-219 - Graham A. Jullien, William C. Miller:
Application of the residue number system to computer processing of digital signals. 220-225 - Danny Cohen:
Mathematical approach to iterative computation networks. 226-238 - Earl E. Swartzlander Jr.:
Merged arithmetic for signal processing. 239-244 - Daniel D. Gajski, Louis P. Rubinfield:
Design of arithmetic elements for Burroughs Scientific Processor. 245-256 - Shlomo Waser:
Survey of arithmetic integrated circuits. 257-266 - Sigurd L. Lillevik, P. David Fisher:
Computational design alternatives with microprocessor-based systems. 267-273
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