default search action
4th Asian Test Symposium 1995: Bangalore, India
- 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India. IEEE Computer Society 1995, ISBN 0-8186-7129-7
Systems Test
- Oum-El-Kheir Benkahla, Chouki Aktouf, Chantal Robach:
Distributed off-line testing of parallel systems. 2-8 - H. A. Xie, Kevin E. Forward, K. M. Adams, Suthikshn Kumar:
An SBus Multi-Tracer and its applications. 9-14 - Yoon-Hwa Choi, Chul Kim:
Exploitation of parallelism in group probing for testing massively parallel processing systems. 15-19 - Naotake Kamiura, Yutaka Hata, Kazuharu Yamato:
A cellular array designed from a Multiple-valued Decision Diagram and its fault tests. 20-
Analysis Techniques
- Yinghua Min, Zhuxing Zhao, Zhongcheng Li:
Boolean process-an analytical approach to circuit representation (II). 26-32 - Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen:
Fanout fault analysis for digital logic circuits. 33-39 - Branka Medved Rogina, Bozidar Vojnovic:
Metastability evaluation method by propagation delay distribution measurement. 40-44 - Zuan Zhang:
An approach to hierarchy model checking via evaluating CTL hierarchically. 45-
Diagnosis
- Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita:
Transistor leakage fault location with ZDDQ measurement. 51-57 - Hiroshi Takahashi, Nobuhiro Yanagida, Yuzo Takamatsu:
Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing. 58-64 - Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey:
A simple technique for locating gate-level faults in combinational circuits. 65-70 - Nabanita Das, Jayasree Dattagupta:
A fault location technique and alternate routing in Benes network. 71-
Fault Simulation
- Eiji Harada, Janak H. Patel:
Overhead reduction techniques for hierarchical fault simulation. 79-85 - Karen Panetta Lentz, Elias S. Manolakos
, Edward C. Czeck:
On the simulation of Multiple Stuck-at Faults using Multiple Domain Concurrent and Comparative Simulation. 86-92 - Chen-Pin Kung, Chun-Jieh Huang, Chen-Shang Lin:
Fast fault simulation for BIST applications. 93-99 - Michel Renovell, P. Huc, Yves Bertrand:
Serial transistor network modeling for bridging fault simulation. 100-106 - Winfried Hahn, Andreas Hagerer, R. Kandlbinder:
Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computing. 107-
Mixed-Signal Test
- Michel Renovell, Florence Azaïs, Yves Bertrand:
A design-for-test technique for multistage analog circuits. 113-119 - Yeong-Ruey Shieh, Cheng-Wen Wu:
DC control and observation structures for analog circuits. 120-126 - Janusz Rzeszut, Bozena Kaminska, Yvon Savaria:
A new method for testing mixed analog and digital circuits. 127-132 - Abu Khari bin A'Ain, A. H. Bratt, A. P. Dorey:
On the development of power supply voltage control testing technique for analogue circuits. 133-139 - Hassan Ihs, Christian Dufaza:
Tolerance DC bands of CMOS operational amplifier. 140-
Design for Testability
- Sukumar Nandi, Parimal Pal Chaudhuri:
Theory and applications of cellular automata for synthesis of easily testable combinational logic. 146-152 - Seiken Yano:
Unified scan design with scannable memory arrays. 153-159 - S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault:
Test configurations to enhance the testability of sequential circuits. 160-168 - Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
Test sequence compaction by reduced scan shift and retiming. 169-175 - Debesh K. Das, Bhargab B. Bhattacharya:
Testable design of non-scan sequential circuits using extra logic. 176-
Education and Research in Testing
- Sudhir K. Jhajharia, Hua Swee Wang:
Training diploma students on ATE-related module. 184-
Panel
- Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, Parimal Pal Chaudhuri:
Panel: New Research Problems in the Emerging Test Technology. 189-190
Testability Measures
- C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal:
A STAFAN-like functional testability measure for register-level circuits. 192-198 - Shiyi Xu, Gercy P. Dias:
Testability forecasting for sequential circuits. 199-205 - Yves Le Traon, Chantal Robach:
Testability analysis of co-designed systems. 206-
Delay Test I
- Jacob Savir:
Generator choices for delay test. 214-221 - Irith Pomeranz, Sudhakar M. Reddy:
Static compaction for two-pattern test sets. 222-228 - Wen Ching Wu, Chung-Len Lee, Jwu E. Chen:
Identification of robust untestable path delay faults. 229-
ATPG
- Dhruva R. Chakrabarti, Ajai Jain:
An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits. 237-243 - Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck:
Deterministic test generation for non-classical faults on the gate level. 244-251 - Hiroshi Date, Michinobu Nakao, Kazumi Hatayama:
A parallel sequential test generation system DESCARTES based on real-valued logic simulation. 252-258 - Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto:
Universal test complexity of field-programmable gate arrays. 259-265 - Arun Balakrishnan, Srimat T. Chakradhar:
Software transformations for sequential test generation. 266-
BIST
- Jacob Savir:
Module level weighted random patterns. 274-278 - Meng-Lieh Sheu, Chung-Len Lee:
A programmable multiple-sequence generator for BIST applications. 279-285 - Jing-Yang Jou:
An effective BIST design for PLA. 286-292 - Manoj Franklin:
Fast computation of C-MISR signatures. 293-297 - Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
An effective BIST scheme for carry-save and carry-propagate array multipliers. 298-302 - Serge N. Demidenko, Alexander Ivanyukovich, Leonid Makhnist
Error masking in compact testing based on the Hamming code and its modifications. 303-
Self-Checking Circuits
- Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis:
An efficient comparative concurrent Built-In Self-Test technique. 309-315 - Nikolaos Gaitanis, Panagiotis Kostarakis, Antonis M. Paschalis:
Totally Self Checking reconfigurable duplication system with separate internal fault indication. 316-321 - Gosta Pada Biswas, Idranil Sen Gupta:
Generalized modular design of testable m-out-of-n code checker. 322-326 - Fadi Y. Busaba, Parag K. Lala:
A graph coloring based approach for self-checking logic circuit design. 327-
Delay Test II
- Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu:
Generation of tenacious tests for small gate delay faults in combinational circuits. 332-338 - Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell:
Functional test generation for path delay faults. 339-345 - Jason P. Hurst, Nick Kanopoulos:
Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits. 346-352 - Soumitra Bose, Vishwani D. Agrawal:
Sequential logic path delay test generation by symbolic analysis. 353-
Technology-Specific Test
- Hiroaki Ueda, Kozo Kinoshita:
Low power design and its testability. 361-366 - Jian Liu, Rafic Z. Makki:
Power supply current detectability of SRAM defects. 367-
Design-Specific Test
- Sandeep Pagey:
Fast functional testing of delay-insensitive circuits. 375-381 - Sandeep Pagey, Ajay Khoche, Erik Brunvand:
DFT for fast testing of self-timed control circuits. 382-386 - Mallika De, Bhabani P. Sinha:
Testing of a parallel ternary multiplier using I2L logic. 387-
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-17 21:05 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: