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NORCAS 2016: Copenhagen, Denmark
- IEEE Nordic Circuits and Systems Conference, NORCAS 2016, Copenhagen, Denmark, November 1-2, 2016. IEEE 2016, ISBN 978-1-5090-1095-0
- Teerasak Lee
, Henry Kennedy, R. A. Bodnar, William Redman-White:
A CMOS MF energy harvesting and data demodulator receiver for wide area low duty cycle applications with 230 mV start-up voltage. 1-4 - Ludwig Karsthof, Mingjie Hao, Jochen Rust
Dynamically reconfigurable real-time hardware architecture for channel utilisation analysis in industrial wireless communication. 1-6 - Tomás Grimm, Djones Lettnin, Michael Hübner:
Automatic generation of RTL connectivity checkers from SystemC TLM and IP-XACT descriptions. 1-6 - Kui Wang, Jari Nurmi
Using OpenCL to rapidly prototype FPGA designs. 1-6 - Alessandro Palla
Area and power consumption trade-off for Σ-Δ decimation filter in mixed signal wearable IC. 1-5 - Martti Forsell, Jussi Roivainen, Ville Leppänen
The REPLICA on-chip network. 1-6 - Pere Llimos Muntal
A 10 MHz bandwidth continuous-time delta-sigma modulator for portable ultrasound scanners. 1-5 - Dmitry Osipov, Steffen Paul, Serge Strokov, Andreas K. Kreiter, Andreas Schander
Current driver with read-out HV protection for neural stimulation. 1-4 - Chih-Yu Chang, Yu-Cheng Li, Nae-Chyun Chen
A special processor design for Nucleotide Basic Local Alignment Search Tool with a new Banded two-hit method. 1-5 - Shailesh Singh Chouhan
Performance evaluation of classical differential rectifier by using forward body biasing technique. 1-4 - Sebastian Haas, Oliver Arnold, Stefan Scholze, Sebastian Höppner, Georg Ellguth, Andreas Dixius, Annett Ungethüm, Eric Mier, Benedikt Noethen, Emil Matús, Stefan Schiefer, Love Cederstroem, Fabian Pilz, Christian Mayr, René Schüffny, Wolfgang Lehner
A database accelerator for energy-efficient query processing and optimization. 1-5 - Faizan Ul Haq, Mikko Englund, Kari Stadius, Marko Kosunen
A wideband blocker-resilient RF front-end with selective input-impedance matching for direct-ΔΣ-receiver architectures. 1-4 - Janne Virtanen, Panu Sjovall
Distributed systemc simulation on manycore servers. 1-6 - Shailesh Singh Chouhan
Voltage multiplier arrangement for heavy load conditions in RF energy harvesting. 1-5 - Farid Shamani, Vida Fakour Sevom
FPGA implementation and integration of a reconfigurable CAN-based co-processor to the coffee risc processor. 1-6 - Kei Ikeda, Atsuki Kobayashi, Kazuo Nakazato, Kiichi Niitsu
A current-mode analog-to-time converter with short-pulse output capability using local intra-cell activation for high-speed time-domain biosensor array. 1-6 - Shiva Jamali-Zavareh, Jarno Salomaa
A 1.3-μW 12-bit incremental ΔΣ ADC for energy harvesting sensor applications. 1-4 - Shadi M. Harb, William R. Eisenstadt
Oscillation ring testing methodology of TSVs in 3D stacked ICs. 1-4 - Lukas Straczek, Thomas Maeke, Dominic A. Funke, Abhishek Sharma
A CMOS 16k microelectrode array as docking platform for autonomous microsystems. 1-6 - Vishnu Unnikrishnan
Design of a VCO-based ADC in 28 nm CMOS. 1-4 - Peter Malík:
Natural logarithm and division floating-point high throughput co-processor implemented in FPGA. 1-6 - Frederik Monrad Spliid, Dennis Oland Larsen, Arnold Knott
Area-efficiency trade-offs in integrated switched-capacitor DC-DC converters. 1-5 - Juan Cartagena, Héctor Gómez, Elkim Roa
A fully-synthesized TRNG with lightweight cellular-automata based post-processing stage in 130nm CMOS. 1-5 - Jianwei Zhang, Shanxing Zheng, Fei Teng, Qiuhong Ding, Xiaoming Chen:
An OR-type cascaded match line scheme for high-performance and EDP-efficient ternary content addressable memory. 1-6 - Lukas Frager, Oner Hanay, Erkan Bayram, Renato Negra:
13-Bit RF-DAC up to 14GS/s at 3.5 GHz introducing Smart-Switching. 1-4 - Priit Ruberg
Data type dependent energy consumption estimation. 1-5 - Keisuke Mashita, Anju Hirota, Tomoaki Tsumura:
Exclusive control for compound operations on hardware transactional memory. 1-6 - Gürkan Yilmaz, Catherine Dehollain:
20-300 MHz frequency generator with -70 dBc reference spur for low jitter serial applications. 1-4 - Ivan Stoychev, Philipp Wehner, Jens Rettkowski, Tobias Kalb, Diana Göhringer
Sensor data fusion with MPSoCSim in the context of electric vehicle charging stations. 1-6 - Joonas Multanen, Heikki Kultala
OpenCL programmable exposed datapath high performance low-power image signal processor. 1-6 - Saam Iranmanesh
Optimizing simulation times in biomedical systems containing Quasi-Infinite Resistors. 1-4 - Lei Zou, Marco De Blasi, Gino Rocca, Marco Grassi
Fully integrated triple-mode sigma-delta modulator for speech codec. 1-4 - Yoni Yosef-Hay, Pere Llimos Muntal
Capacitor-free, low drop-out linear regulator in a 180 nm CMOS for hearing aids. 1-5 - Héctor Gómez, Andres Amaya, Elkim Roa
DRAM row-hammer attack reduction using dummy cells. 1-4 - Awais Hussain Sani, José Luis Núñez-Yáñez
Energy proportional computing with OpenCL on a FPGA-based overlay architecture. 1-6 - Jochen Rust
Bivariate function approximation with encoded gradients. 1-6 - Stefan Muller
Current-steering DAC linearisation by impedance transformation. 1-4 - Erkan Bayram, Oner Hanay, Renato Negra:
A 4.5 mW, 0.01148 mm2 frequency multiplier based on DLL with output frequency from 4 to 6 GHz. 1-4 - Emmanuel Ovie Osimiry, Raimund Ubar
A novel random approach to diagnostic test generation. 1-4 - Syed Abbas Ali Shah, Bastian Farkas, Rolf Meyer, Mladen Berekovic
Accelerating MPSoC design space exploration within system-level frameworks. 1-6 - Christian Menard
High-level NoC model for MPSoC compilers. 1-6 - Arnout Devos, Marco Vigilante, Patrick Reynaert
Multiphase digitally controlled oscillator for future 5G phased arrays in 90 nm CMOS. 1-4 - Xinyu Ma, Sebastian Bader, Bengt Oelmann:
Solar panel modelling for low illuminance indoor conditions. 1-6 - Wei Zhang, Youde Hu, Yuxiang Huan, Zhuo Zou, Keji Cui, Dongxuan Bao, Dashan Pan, Lebo Wang, Li-Rong Zheng:
Hierarchical design of a low power standing wave oscillator based clock distribution network. 1-5 - Kairang Chen, Martin Nielsen-Lönn
Asynchronous clock generator for a 14-bit two-stage pipelined SAR ADC in 0.18 μm CMOS. 1-4 - Federico Pepe
An experimental comparison between two widely adopted phase noise models. 1-4 - Jonathan Taylor, Alberto Nannarelli
Design and simulation of a quaternary memory cell based on a physical memristor. 1-6 - Tuan Nguyen Gia
IoT-based fall detection system with energy efficient sensor nodes. 1-6 - Felix Neumärker, Sebastian Höppner, Andreas Dixius, Christian Mayr:
True random number generation from bang-bang ADPLL jitter. 1-5 - Mohd Amiruddin Zainol, José Luis Núñez-Yáñez
CPCIe: A compression-enabled PCIe core for energy and performance optimization. 1-6 - Ali Asghar Vatanjou, Even Låte, Trond Ytterdal, Snorre Aunet:
Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing. 1-4 - Robert Kostack, Christoph Tzschoppe, Herbert Stockinger, Udo Jörges, Frank Ellinger:
A 2 GHz low noise amplifier with transformer input matching in 28 nm CMOS. 1-6
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