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1. Nano-Net 2006: Lausanne, Switzerland
- Gian Mario Maggio, Chris Dwyer:
1st International ICST Conference on Nano-Networks, Nano-Net 2006, Lausanne, Switzerland, September 14-16, 2006. IEEE 2006, ISBN 1-4244-0391-X - Luke Demoracski, Fabrizio Lombardi:
Connecting and Configuring Defective Nano-Scale Networks for DNA Self-Assembly. 1-5 - Dongkook Park, Chrysostomos Nicopoulos
, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das:
A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects. 1-6 - Davide Franceschini, Massimo Donelli
Future Trends on Nanoantennas Synthesis. 1-5 - Paolo Meloni
Area and Power Modeling Methodologies for Networks-on-Chip. 1-7 - Paolo Meloni
Routing Aware Switch Hardware Customization for Networks on Chips. 1-5 - Aranggan Venkataratnam, Ashok K. Goel:
Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional Devices. 1-5 - Ivan Miro Panades, Alain Greiner, Abbas Sheibanyrad:
A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach. 1-5 - Eric Rotenberg, Ravi V. Venkatesan:
The State of ZettaRAM. 1-5 - Hideaki Matsueda:
Multipolar Photonic Interactions for Interconnections and Logical Operations in Nanostructure Networks. 1-5 - Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck:
Self-Assembled Networks: Control vs. Complexity. 1-5 - Benjamin Gojman, Raphael Rubin, Concetta Pilotto, André DeHon, Tetsufumi Tanamoto:
3D Nanowire-Based Programmable Logic. 1-5 - Sandro Carrara, Bruno Samorì, Sigrid Bernstorff
Hybrid Nanostructures: Organic Interconnections and Device Applications. 1-5 - Sachin Sonkusale, Paul D. Franzon
Controlled nanowire fabrication by PEDAL process. 1-8 - Kumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon:
Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. 1-5 - Yu Cao, Wei Zhao:
Predictive Technology Model for Nano-CMOS Design Exploration. 1-5 - Joseph W. Tringe, Warren MoberlyChan, Charles Stevens, Albert Davydov, Abhishek Motayed:
Electron Beam-induced Light Emission and Transport in GaN Nanowires. 1-4 - Paul P. Sotiriadis
Nanoscale Data Storage Devices Capacity and Encoding Schemes. 1-4 - Paul Bogdan
A Theoretical Framework for On-chip Stochastic Communication Analysis. 1-5 - Giuseppa Alfano
On Information Transmission Among Nanomachines. 1-5 - Wei Wang, Adam Maina Ari, Woon Ket Wong:
On-Chip Interconnects and Repeaters Based on NiSi Nanowires. 1-5 - Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee:
3D on-chip networking technology based on post-silicon devices for future networks-on-chip. 1-5 - Stephen F. Bush
Graph Spectra of Carbon Nanotube Networks. 1-10 - Kaustav Banerjee, Sungjun Im, Navin Srivastava:
Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections? 1-9 - Daniele Mangano, Riccardo Locatelli, Alberto Scandurra, Carlo Pistritto, Marcello Coppola
Skew Insensitive Physical Links for Network on Chip. 1-5 - Amir Hosseini, Arthur Nieuwoudt, Yehia Massoud:
Optimizing Dielectric Strip Plasmonic Waveguides for Subwavelength On-Chip Optical Communication. 1-5 - Mosin Mondal, Xiang Wu, Adnan Aziz, Yehia Massoud:
Reliability Analysis for On-chip Networks under RC Interconnect Delay Variation. 1-5 - Yehia Massoud, Arthur Nieuwoudt:
Modeling and Evaluating Carbon Nanotube Bundles for Future VLSI Interconnect Applications. 1-5 - Alberto Scandurra, Maurizio Lenzi, Ranieri Guerra, Francesco Giuseppe Della Corte, Maria Arcangela Nigro:
Optical Interconnects for Network on Chip. 1-5
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