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14th MCSoC 2021: Singapore
- 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2021, Singapore, Singapore, December 20-23, 2021. IEEE 2021, ISBN 978-1-6654-3860-5
- Iman Firmansyah
, Yoshiki Yamaguchi:
FPGA-Based Implementation of the Stereo Matching Algorithm Using High-Level Synthesis. 1-7 - Fumiya Kono, Naohito Nakasato, Naru Hirata, Koji Matsumoto:
Acceleration of Gravitation Field Analysis for Asteroids by GPU Computation. 8-15 - Dongkyu Jung, Daejin Park:
Accelerated on-Chip Algorithm Based on Semantic Region-Based Partial Difference Detection for LiDAR-Vision Depth Data Transmission Reduction in Lightweight Controller Systems of Autonomous Vehicle. 16-22 - Ralf Kundel
Host Bypassing: Direct Data Piping from the Network to the Hardware Accelerator. 23-30 - Takashi Odan, Takuto Kanamori, Kenji Kise:
A function-rich FPGA system of camera image processing for video meeting. 31-37 - Takuto Kanamori, Kenji Kise:
RVCoreP-32IC: An optimized RISC- V soft processor supporting the compressed instructions. 38-45 - Takaharu Suzuki, Kiyofumi Tanaka:
Execution Right Delegation Scheduling Algorithm for Multiprocessor. 46-53 - Julius Roeder, Benjamin Rouxel, Clemens Grelck:
Scheduling DAGs of Multi-Version Multi-Phase Tasks on Heterogeneous Real-Time Systems. 54-61 - Aurelien Bloch
SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis. 62-68 - Aurelien Bloch
Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms. 69-76 - Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano:
Parallel Implementation of CNN on Multi-FPGA Cluster. 77-83 - Fumio Hamanaka, Takuto Kanamori, Kenji Kise:
A Low Cost and Portable Mini Motor Car System with a BNN Accelerator on FPGA. 84-91 - Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu:
A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once- Write Shifting. 92-97 - Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura
Multi-objective Reinforcement Learning for Energy Harvesting Wireless Sensor Nodes. 98-105 - Zhenshan Bao, Junnan Guo, Xiaqing Li, Wenbo Zhang:
MSCU: Accelerating CNN Inference with Multiple Sizes of Compute Unit on FPGAs. 106-113 - Risikesh RK, Sharad Sinha, Nanditha P. Rao:
Variable Bit-Precision Vector Extension for RISC-V Based Processors. 114-121 - Tiancheng Cao, Chen Liu, Yuan Gao, Wang Ling Goh:
Parasitic-Aware Modelling for Neural Networks Implemented with Memristor Crossbar Array. 122-126 - Haklin Kimm, Incheon Paik:
Distributed Neural Network with TensorFlow on Human Activity Recognition Over Multicore TPU. 127-134 - Yuta Kasuga, Jungpil Shin, Md. Al Mehedi Hasan, Yuichi Okuyama, Yoichi Tomioka
EEG-based Positive-Negative Emotion Classification Using Machine Learning Techniques. 135-139 - Toshihiro Uetsuki, Yuichi Okuyama, Jungpil Shin:
CNN-based End-to-end Autonomous Driving on FPGA Using TVM and VTA. 140-144 - Md. Al Mehedi Hasan, Fuad Al Abir, Jungpil Shin:
Surface Type Classification for Autonomous Robots Using Temporal, Statistical and Spectral Feature Extraction and Selection. 145-150 - Maoyang Xiang, Tee Hui Teo:
A Multi-scale Binarized Neural Network Application Based on All Programmable System on Chip. 151-156 - Albert Budi Christian, Chih-Yu Lin, Lan-Da Van, Yu-Chee Tseng:
Data Fusion Driven Lane-level Precision Data Transmission for V2X Road Applications. 157-163 - Zikang Zhou, Chao Fu, Ruiqi Xie, Jun Han:
A Heterogeneous Full-stack AI Platform for Performance Monitoring and Hardware-specific Optimizations. 164-170 - Lan-Da Van, Tao-Jung Wang, Sing-Jia Tzeng, Tzyy-Ping Jung
A Computation-Aware TPL Utilization Procedure for Parallelizing the FastICA Algorithm on a Multi-Core CPU. 171-177 - Kaisei Shimura, Yoichi Tomioka
A Distance Estimation Method to Railway Crossing Using Warning Signs. 178-181 - Kungan Zeng, Incheon Paik:
Dynamic Service Recommendation Using Lightweight BERT-based Service Embedding in Edge Computing. 182-189 - Hongbo Chen, Lei Jing:
Light-weight Enhanced Semantics-Guided Neural Networks for Skeleton-Based Human Action Recognition. 190-196 - Masahito Kumagai, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi:
Ising-Based Combinatorial Clustering Using the Kernel Method. 197-203 - Yufan Lu, Xiaojun Zhai, Sangeet Saha, Shoaib Ehsan, Klaus D. McDonald-Maier:
FPGA based Adaptive Hardware Acceleration for Multiple Deep Learning Tasks. 204-209 - Pavitra Prakash Bhade, Sharad Sinha:
Detection of Cache Side Channel Attacks Using Thread Level Monitoring of Hardware Performance Counters. 210-217 - Michael J. Giardino, Daniel Schwyn
2QoSM: A Q-Learner QoS Manager for Application-Guided Power-Aware Systems. 218-225 - Parisa Rahimi, Amit Kumar Singh, Xiaohang Wang, Alok Prakash:
Trends and Challenges in Ensuring Security for Low-Power and High-Performance Embedded SoCs. 226-233 - Daichi Mukunoki
Task Scheduling Strategies for Batched Basic Linear Algebra Subprograms on Many-core CPUs. 234-241 - Shunpei Sugawara, Yoichi Shimomura, Ryusuke Egawa, Hiroyuki Takizawa
Portability of Vectorization-aware Performance Tuning Expertise across System Generations. 242-248 - Younghyun Cho, James Demmel, Xiaoye S. Li, Yang Liu, Hengrui Luo:
Enhancing Autotuning Capability with a History Database. 249-257 - Tomoko Komiyama, Tomohiro Suzuki:
Sparse Matrix Ordering Method with a Quantum Annealing Approach and its Parameter Tuning. 258-264 - Tanvir Ahmed, Johannes Maximilian Kühn, Ken Namura:
A Highly Efficient Layout-Aware FPGA Overlay Accelerator Mapping Method. 265-272 - Aika Kamei
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops. 273-280 - Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Multiport Register File Design for High-Performance Embedded Cores. 281-286 - Md. Atiqur Rahman, Mohamed Hamada, Md. Asfaqur Rahman:
Text Compression Based on an Alternative Approach of Run-Length Coding Using Burrows-Wheeler Transform and Arithmetic Coding. 287-291 - Toru Tamahashi, Rentaro Yoshioka
UI Method to Support Knowledge Creation in Hybrid Museum Experience. 292-295 - Takayuki Hoshino, Rentaro Yoshioka
Design of a Knowledge Experience Based Environment for Museum Data Exploration and Knowledge Creation. 296-303 - Yohei Shimmyo, Yuichi Okuyama:
Mini-Batch Training along Convolution Windows for Representation Learning Based on Spike-Time-Dependent-Plasticity Rule. 304-311 - Haklin Kimm, Incheon Paik, Hanke Kimm:
Performance Comparision of TPU, GPU, CPU on Google Colaboratory Over Distributed Deep Learning. 312-319 - R. Kleijnen
A Network Simulator for the Estimation of Bandwidth Load and Latency Created by Heterogeneous Spiking Neural Networks on Neuromorphic Computing Communication Networks. 320-327 - Evelina Forno, Andrea Spitale, Enrico Macii, Gianvito Urgese:
Configuring an Embedded Neuromorphic Coprocessor Using a RISC-V Chip for Enabling Edge Computing Applications. 328-332 - Mohamed Hamada, Jesse Jeremiah Tanimu, Mohammed Hassan, Habeebah Adamu Kakudi, Patience Robert:
Evaluation of Recursive Feature Elimination and LASSO Regularization-based optimized feature selection approaches for cervical cancer prediction. 333-339 - Egwom Onyinyechi Jessica
The Role of Linear Discriminant Analysis for Accurate Prediction of Breast Cancer. 340-344 - Aminu Musa, Mohamed Hamada, Farouq Muhammad Aliyu, Mohammed Hassan:
An Intelligent Plant Dissease Detection System for Smart Hydroponic Using Convolutional Neural Network. 345-351 - Atsushi Takamiya, Md. Mostafizer Rahman
A Framework and Its User Interface to Learn Machine Learning Models. 352-358 - Mong Tee Sim:
Boosting CPU Performance using Pipelined Branch and Jump Folding Hardware with Turbo Module. 359-365 - Md. Ashraful Islam, Kenji Kise:
Efficient Resource Shared RISC-V Multicore Processor. 366-372 - Lukas Miedema
Task-level Redundancy vs Instruction-level Redundancy against Single Event Upsets in Real-time DAG scheduling. 373-380 - Richard Fenster, Sébastien Le Beux:
RELAX: a REconfigurabLe Approximate Network-on-Chip. 381-387 - Saeid Dehnavi, Dip Goswami, Kees Goossens:
Analyzable Publish-Subcribe Communication Through a Wait-Free FIFO Channel for MPSoC Real-Time Applications. 388-395 - Vasco Miguel Liang Xu, Liam White McShane, Daniel Mossé:
LUSH: Lightweight Framework for User-level Scheduling in Heterogeneous Multicores. 396-404 - Octavio Delgadillo
An Architecture to Enable Machine-Learning-Based Task Migration for Multi-Core Real-Time Systems. 405-412
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