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Low Power Networks-on-Chip 2011
- Cristina Silvano
, Marcello Lajolo, Gianluca Palermo
Low Power Networks-on-Chip. Springer 2011, ISBN 978-1-4419-6910-1
Low-Level Design Techniques
- Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, Shekhar Y. Borkar:
Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections. 3-20 - Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura
Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. 21-43 - Paul Ampadu, Bo Fu, David Wolpert, Qiaoyan Yu:
Adaptive Voltage Control for Energy-Efficient NoC Links. 45-69 - Stanislavs Golubcovs, Alex Yakovlev
Asynchronous Communications for NoCs. 71-109
System-Level Design Techniques
- Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania:
Application-Specific Routing Algorithms for Low Power Network on Chip Design. 113-150 - Yuho Jin, Ki Hwan Yum, Eun Jung Kim:
Adaptive Data Compression for Low-Power On-Chip Networks. 151-174 - Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny:
Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study. 175-195
Future and Emerging Technologies
- Ciprian Seiculescu, Srinivasan Murali, Luca Benini
Design and Analysis of NoCs for Low-Power 2D and 3D SoCs. 199-222 - Jung Ho Ahn
CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study. 223-254 - Sai-Wang Tam, Eran Socher, Mau-Chung Frank Chang
RF-Interconnect for Future Network-On-Chip. 255-280
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