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"Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint ..."

Satoshi Shigematsu et al. (2007)

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DOI: 10.1093/IETELE/E90-C.10.1892

access: closed

type: Journal Article

metadata version: 2020-04-11

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  - journals/ieicet/ShigematsuMSHIOMN07
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  - https://dblp.org/rec/journals/ieicet/ShigematsuMSHIOMN07
Satoshi Shigematsu, Hiroki Morimura, Toshishige Shimamura, Takahiro Hatano, Namiko Ikeda, Yukio Okazaki, Katsuyuki Machida, Mamoru Nakanishi:
Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI. IEICE Trans. Electron. 90-C(10): 1892-1899 (2007)

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