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"Novel on-chip circuit for jitter testing in high-speed PLLs."

José Manuel Cazeaux, Martin Omaña, Cecilia Metra (2005)

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DOI: 10.1109/TIM.2005.855104

access: closed

type: Journal Article

metadata version: 2022-11-20

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  - https://dblp.org/rec/journals/tim/CazeauxOM05
José Manuel Cazeaux, Martin Omaña, Cecilia Metra:
Novel on-chip circuit for jitter testing in high-speed PLLs. IEEE Trans. Instrum. Meas. 54(5): 1779-1788 (2005)

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