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"A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip ..."

Shunli Ma et al. (2019)

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DOI: 10.1109/TCSI.2018.2867623

access: closed

type: Journal Article

metadata version: 2020-05-22

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  - https://dblp.org/rec/journals/tcas/Ma0GR19
Shunli Ma, Hao Yu, Qun Jane Gu, Junyan Ren:
A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 555-568 (2019)

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