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"Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm ..."

Rohit Pandey, Santanu Chattopadhyay (2003)

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DOI: 10.1109/ICVD.2003.1183118

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Rohit Pandey, Santanu Chattopadhyay:
Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach". VLSI Design 2003: 79-84

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