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"Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based ..."

Gianpiero Cabodi et al. (2016)

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DOI: 10.1109/FMCAD.2016.7886657

access: closed

type: Conference or Workshop Paper

metadata version: 2019-12-27

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  - conf/fmcad/CabodiCPPV16
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Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto:
Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening. FMCAD 2016: 25-32

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