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"A ring-VCO-based sub-sampling PLL CMOS circuit with -119 dBc/Hz phase ..."

Kenta Sogo, Akihiro Toya, Takamaro Kikkawa (2012)

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DOI: 10.1109/ESSCIRC.2012.6341333

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Kenta Sogo, Akihiro Toya, Takamaro Kikkawa:
A ring-VCO-based sub-sampling PLL CMOS circuit with -119 dBc/Hz phase noise and 0.73 ps jitter. ESSCIRC 2012: 253-256

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