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"A global bus power optimization methodology for physical design of memory ..."

Hua Wang et al. (2004)

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DOI: 10.1109/ASPDAC.2004.17

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/aspdac/WangPMC04
Hua Wang, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor:
A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement. ASP-DAC 2004: 759-761

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