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"Topology-related effects of Gated-Vdd and Gated-Vss techniques on ..."

Pradeep S. Nair, Savithra Eratne, Eugene John (2008)

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DOI: 10.1109/APCCAS.2008.4746186

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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Pradeep S. Nair, Savithra Eratne, Eugene John:
Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm. APCCAS 2008: 972-975

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