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Bo-Cheng Lai
Bo-Cheng Charles Lai
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- affiliation: University of California, Los Angeles, USA
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2020 – today
- 2024
- [c48]Yi-Ting Wu, Tzu-Yun Yen, Yu-Pei Lin, Bo-Cheng Lai:
HeteroEML: Heterogeneous Design Methodology of Edge Machine Learning on CPU+FPGA Platform. AICAS 2024: 16-20 - [c47]Bo-Han Li, Kuan-Chih Lin, Hao Zuo, Po-Cheng Pan, Hung-Ming Chen, Shyh-Jye Jou, Chien-Nan Jimmy Liu, Bo-Cheng Lai:
Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization. MWSCAS 2024: 1085-1090 - [i6]Xiaohan Liu, ChiJui Chen, YanLun Huang, LingChi Yang, Elham E Khoda, Yihui Chen, Scott Hauck, Shih-Chieh Hsu, Bo-Cheng Lai:
FPGA Deployment of LFADS for Real-time Neuroscience Experiments. CoRR abs/2402.04274 (2024) - [i5]Edwin Arkel Rios, Min-Chun Hu, Bo-Cheng Lai:
Global-Local Similarity for Efficient Fine-Grained Image Recognition with Vision Transformers. CoRR abs/2407.12891 (2024) - [i4]Edwin Arkel Rios, Femiloye Oyerinde, Min-Chun Tien, Bo-Cheng Lai:
Down-Sampling Inter-Layer Adapter for Parameter and Computation Efficient Ultra-Fine-Grained Image Recognition. CoRR abs/2409.11051 (2024) - 2023
- [j23]Aman Sinha
, Bo-Cheng Lai
A Bin-Based Indexing for Scalable Range Join on Genomic Data. IEEE ACM Trans. Comput. Biol. Bioinform. 20(3): 2210-2222 (2023) - [c46]Shi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier M. Duarte
Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs. FPL 2023: 294-298 - [c45]Aman Sinha
REGAL: Reprogrammable Engines for Genome Analysis on LPDDR4x-based Stacked DRAM. ISCAS 2023: 1-5 - [c44]Aman Sinha
GRONA : A Framework for Gather-and-Reduce On Near-Memory Accelerators. MCSoC 2023: 225-232 - [i3]Shi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier M. Duarte, Scott Hauck, Shih-Chieh Hsu, Jin-Xuan Hu, Mark S. Neubauer:
Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs. CoRR abs/2306.11330 (2023) - 2022
- [j22]Aman Sinha
DSIM: Distributed Sequence Matching on Near-DRAM Accelerator for Genome Assembly. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 486-499 (2022) - [j21]Abdelrahman Elabd, Vesal Razavimaleki, Shi-Yu Huang, Javier M. Duarte
Graph Neural Networks for Charged Particle Tracking on FPGAs. Frontiers Big Data 5: 828666 (2022) - [c43]Bo-Cheng Lai, Tzu-Chieh Chiang, Po-Shen Kuo, Wan-Ching Wang, Yan-Lin Hung, Hung-Ming Chen, Chien-Nan Liu, Shyh-Jye Jou:
DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks. DATE 2022: 208-213 - [c42]Edwin Arkel Rios
Anime Character Recognition using Intermediate Features Aggregation. ISCAS 2022: 424-428 - [c41]Bo-Rong Yan, Edwin Arkel Rios
DLPrPPG: Development and Design of Deep Learning Platform for Remote Photoplethysmography. ISCAS 2022: 697-701 - [c40]Po-Yen Lin, Yen-Shi Kuo, Bo-Cheng Lai:
A Highly Parallel Fine-Grained Sort-Merge Join on Near Memory Computing. ISCAS 2022: 2566-2570 - [c39]Aman Sinha
MSIM: A Highly Parallel Near-Memory Accelerator for MinHash Sketch. SOCC 2022: 1-6 - [c38]Yi-Da Hsin, Yen-Shi Kuo, Bo-Cheng Lai:
Distributed Sorting Architecture on Multiple FPGA. VLSI-DAT 2022: 1-4 - 2021
- [c37]Edwin Arkel Rios
Parametric Study of Performance of Remote Photopletysmography System. ISCAS 2021: 1-4 - [c36]Hung-Ming Chen, Cheng-En Ni, Kang-Yu Chang, Tzu-Chieh Chiang, Shih-Han Chang, Cheng-Yu Chiang, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou:
On Reconfiguring Memory-Centric AI Edge Devices for CIM. ISOCC 2021: 262-263 - [c35]Bo-En Chen, Bo-Yen Lin, Bo-Cheng Lai:
Reconfigurable Database Processor for Query Acceleration on FPGA. VLSI-DAT 2021: 1-4 - [i2]Edwin Arkel Rios, Wen-Huang Cheng, Bo-Cheng Lai:
DAF: re: A Challenging, Crowd-Sourced, Large-Scale, Long-Tailed Dataset For Anime Character Recognition. CoRR abs/2101.08674 (2021) - [i1]Abdelrahman Elabd, Vesal Razavimaleki, Shi-Yu Huang, Javier M. Duarte
Graph Neural Networks for Charged Particle Tracking on FPGAs. CoRR abs/2112.02048 (2021) - 2020
- [j20]Bo-Cheng Lai
A Two-Directional BigData Sorting Architecture on FPGAs. IEEE Comput. Archit. Lett. 19(1): 72-75 (2020) - [j19]Duc-An Pham, Bo-Cheng Lai:
Dataflow and microarchitecture co-optimisation for sparse CNN on distributed processing element accelerator. IET Circuits Devices Syst. 14(8): 1185-1194 (2020) - [j18]Moustafa Emara, Bo-Cheng Lai:
Selective bypassing and mapping for heterogeneous applications on GPGPUs. J. Parallel Distributed Comput. 142: 106-118 (2020) - [j17]Chien-Ching Lee, Chia-Chun Chuang, Bo-Cheng Lai, Yi-Chia Huang, Jen-Yin Chen, Bor-Shyh Lin
A Novel Smart Assistance System for Blood Vessel Approaching: A Technical Report Based on Oximetry. Sensors 20(7): 1891 (2020) - [j16]Bo-Cheng Lai
REMAP+: An Efficient Banking Architecture for Multiple Writes of Algorithmic Memory. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 660-671 (2020) - [c34]Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Küster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou:
On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. ICCAD 2020: 127:1-127:8
2010 – 2019
- 2019
- [j15]Bo-Cheng Lai
Enhancing Utilization of SIMD-Like Accelerator for Sparse Convolutional Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1218-1222 (2019) - [c33]Aman Sinha
DP2: A Highly Parallel Range Join for Genome Analysis on Distributed Computing Platform. HPCS 2019: 358-362 - [c32]Bo-Ya Chen, Bo-En Chen, Bo-Cheng Lai:
Efficient Write Scheme for Algorithm-Based Multi-Ported Memory. VLSI-DAT 2019: 1-4 - 2018
- [j14]Bo-Cheng Lai, Tung-Yu Wu, Tsou-Han Chiu, Kun-Chun Li, Chia-Ying Lee, Wei-Chen Chien, Wing Hung Wong:
Towards high performance data analytic on heterogeneous many-core systems: A study on Bayesian Sequential Partitioning. J. Parallel Distributed Comput. 122: 36-50 (2018) - [c31]Chien-Yu Lin, Bo-Cheng Lai:
Supporting compressed-sparse activations and weights on SIMD-like accelerator for sparse convolutional neural networks. ASP-DAC 2018: 105-110 - 2017
- [j13]Bo-Cheng Charles Lai
Efficient Designs of Multiported Memory on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 139-150 (2017) - [j12]Bo-Cheng Charles Lai
An Efficient Hierarchical Banking Structure for Algorithmic Multiported Memory on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2776-2788 (2017) - [c30]Sheng-Yen Chen, Chia-I Wei, Yu-Chen Chiu, Bo-Cheng Charles Lai:
A Hadoop-based Principle Component Analysis on embedded heterogeneous platform. VLSI-DAT 2017: 1-4 - 2016
- [j11]Bo-Cheng Charles Lai, Luis Garrido Platero, Hsien-Kai Kuo:
A Quantitative Method to Data Reuse Patterns of SIMT Applications. IEEE Comput. Archit. Lett. 15(2): 73-76 (2016) - [j10]Bo-Cheng Charles Lai, Chia-Ying Lee, Tsou-Han Chiu, Hsien-Kai Kuo, Chun-Kai Chang:
Unified Designs for High Performance LDPC Decoding on GPGPU. IEEE Trans. Computers 65(12): 3754-3765 (2016) - [c29]Chin-Fu Lu, Hsien-Kai Kuo, Bo-Cheng Charles Lai:
Enhancing Data Reuse in Cache Contention Aware Thread Scheduling on GPGPU. CISIS 2016: 351-356 - 2015
- [j9]Gung-Yu Pan, Chih-Yen Lai, Jing-Yang Jou, Bo-Cheng Charles Lai:
Power-Efficient Instancy Aware DRAM Scheduling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(4): 942-953 (2015) - [j8]Bo-Cheng Charles Lai, Kun-Chun Li, Guan-Ru Li, Chih-Hsuan Chiang:
Self adaptable multithreaded object detection on embedded multicore systems. J. Parallel Distributed Comput. 78: 25-38 (2015) - [j7]Bo-Cheng Charles Lai, Hsien-Kai Kuo, Jing-Yang Jou:
A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs. IEEE Trans. Computers 64(4): 884-898 (2015) - [j6]Gung-Yu Pan, Jed Yang, Jing-Yang Jou, Bo-Cheng Charles Lai:
Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors. ACM Trans. Embed. Comput. Syst. 14(4): 70:1-70:24 (2015) - [j5]Bo-Cheng Charles Lai, Kuan-Ting Chen, Ping-Ru Wu:
A High-Performance Double-Layer Counting Bloom Filter for Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2473-2486 (2015) - [c28]Yun-Ting Wang, Jia-Ying Lee, Bo-Cheng Charles Lai:
Computation and Communication Aware task graph Scheduling on multi-GPU systems. DSP 2015: 115-119 - [c27]Ping-Ju Wu, Chien-Yu Lin, Bo-Cheng Charles Lai:
Design of Application Specific Throughput Processor for Matrix Operations. NBiS 2015: 324-331 - [c26]Jiun-Liang Lin, Bo-Cheng Charles Lai:
BRAM efficient multi-ported memory on FPGA. VLSI-DAT 2015: 1-4 - 2014
- [j4]Gung-Yu Pan, Jing-Yang Jou, Bo-Cheng Lai:
Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors. ACM Trans. Design Autom. Electr. Syst. 19(4): 33:1-33:23 (2014) - [j3]Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou:
Reducing Contention in Shared Last-Level Cache for Throughput Processors. ACM Trans. Design Autom. Electr. Syst. 20(1): 12:1-12:28 (2014) - [c25]Gung-Yu Pan, Bo-Cheng Charles Lai, Sheng-Yen Chen, Jing-Yang Jou:
A learning-on-cloud power management policy for smart devices. ICCAD 2014: 376-381 - [c24]Ta Kang Yen, Bo Yao Yu, Bo-Cheng Charles Lai:
A Cache Aware Multithreading Decision Scheme on GPGPUs. MCSoC 2014: 267-272 - [c23]Ying-Yu Tseng, Yu-Hao Huang, Bo-Cheng Charles Lai, Jiun-Liang Lin:
Automatic Data Layout Transformation for Heterogeneous Many-Core Systems. NPC 2014: 208-219 - 2013
- [c22]Hsien-Kai Kuo, Ta-Kan Yen, Bo-Cheng Charles Lai, Jing-Yang Jou:
Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs. ASP-DAC 2013: 338-343 - [c21]Yu-Hao Huang, Ying-Yu Tseng, Hsien-Kai Kuo, Ta-Kan Yen, Bo-Cheng Charles Lai:
A Locality-Aware Dynamic Thread Scheduler for GPGPUs. PDCAT 2013: 254-258 - [c20]Hao-Wei Liu, Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai:
Memory capacity aware non-blocking data transfer on GPGPU. SiPS 2013: 395-400 - [c19]Ta-Kan Yen, Hsien-Kai Kuo, Bo-Cheng Charles Lai:
A distributed thread scheduler for dynamic multithreading on throughput processors. VLSI-DAT 2013: 1-4 - 2012
- [c18]Tsou-Han Chiu, Hsien-Kai Kuo, Bo-Cheng Charles Lai:
A highly parallel design for irregular LDPC decoding on GPGPUs. APSIPA 2012: 1-5 - [c17]Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai, Jing-Yang Jou:
Thread affinity mapping for irregular data access on shared Cache GPGPU. ASP-DAC 2012: 659-664 - [c16]Kuan-Ting Chen, Ping-Ru Wu, Bo-Cheng Charles Lai:
Reduce Data Coherence Cost with an Area Efficient Double Layer Counting Bloom Filter. PAAP 2012: 7-12 - [c15]Guan-Ru Li, Bo-Cheng Charles Lai:
A highly parallel design of image surface layout recovering on GPGPU. VLSI-DAT 2012: 1-4 - 2011
- [c14]Bo-Cheng Charles Lai, Chih-Hsuan Chiang, Guan-Ru Li:
Classifier Grouping to Enhance Data Locality for a Multi-threaded Object Detection Algorithm. ICPADS 2011: 268-275 - 2010
- [c13]Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou:
Unleash the parallelism of 3DIC partitioning on GPGPU. SoCC 2010: 127-132
2000 – 2009
- 2008
- [j2]Jongsun Kim, Bo-Cheng Lai, Mau-Chung Frank Chang
A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems. IEEE Trans. Computers 57(12): 1714-1719 (2008) - 2006
- [j1]David D. Hwang, Kris Tiri, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks. IEEE J. Solid State Circuits 41(4): 781-792 (2006) - [c12]Bo-Cheng Charles Lai, Patrick Schaumont
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip. ASAP 2006: 15-18 - 2005
- [c11]Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede:
Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. CHES 2005: 354-365 - [c10]Patrick Schaumont
Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design. DAC 2005: 27-30 - [c9]Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. DAC 2005: 222-227 - [c8]Alireza Hodjat, David Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede:
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology. ACM Great Lakes Symposium on VLSI 2005: 60-63 - [c7]Bo-Cheng Charles Lai, Patrick Schaumont
Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System. ICCD 2005: 102-104 - [p1]Ingrid Verbauwhede
Security for Ambient Intelligent Systems. Ambient Intelligence 2005: 199-221 - 2004
- [c6]David Hwang, Bo-Cheng Lai, Ingrid Verbauwhede:
Energy-Memory-Security Tradeoffs in Distributed Sensor Networks. ADHOC-NOW 2004: 70-81 - [c5]Bo-Cheng Lai, David Hwang, Sungha Pete Kim, Ingrid Verbauwhede
Reducing radio energy consumption of key management protocols for wireless sensor networks. ISLPED 2004: 351-356 - 2003
- [c4]Tim Tuan, Bo-Cheng Lai:
Leakage power analysis of a 90nm FPGA. CICC 2003: 57-60 - [c3]David D. Hwang, Bo-Cheng Lai, Patrick Schaumont
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system. DAC 2003: 60-65 - [c2]Patrick Schaumont
Testing ThumbPod: Softcore bugs are hard to find. HLDVT 2003: 77-82 - 2002
- [c1]David Hwang, Bo-Cheng Lai, Patrick Schaumont, Ingrid Verbauwhede:
A Security Protocol for Biometric Smart Cards. CARDIS 2002
Coauthor Index
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