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Marcelo O. Johann
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- affiliation: Federal University of Rio Grande do Sul, Porto Alegre, Brazil
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2010 – 2019
- 2019
- [j6]Jucemar Monteiro, Marcelo O. Johann, Laleh Behjat
:
An Optimized Cost Flow Algorithm to Spread Cells in Detailed Placement. ACM Trans. Design Autom. Electr. Syst. 24(3): 35:1-35:16 (2019) - [c39]Filipe Lins, Marcelo O. Johann, Emmanouil Benetos
Automatic Transcription of Diatonic Harmonica Recordings. ICASSP 2019: 256-260 - 2018
- [c38]Rodrigo Schramm, Federico Visi, André Brasil, Marcelo O. Johann:
A polyphonic pitch tracking embedded system for rapid instrument augmentation. NIME 2018: 120-125 - 2017
- [c37]Guilherme Flach, Mateus Fogaça
Rsyn: An Extensible Physical Synthesis Framework. ISPD 2017: 33-40 - 2016
- [c36]Mateus Fogaça
Quadratic timing objectives for incremental timing-driven placement optimization. ICECS 2016: 620-623 - [c35]Guilherme Flach, Mateus Fogaça
Drive Strength Aware Cell Movement Techniques for Timing Driven Placement. ISPD 2016: 73-80 - [c34]Jucemar Monteiro, Nima Karimpour Darav, Guilherme Flach, Mateus Fogaça
Routing-Aware Incremental Timing-Driven Placement. ISVLSI 2016: 290-295 - [c33]Mateus Fogaça
Improving placement algorithms by using visualization tools. NEWCAS 2016: 1-4 - 2015
- [c32]Jucemar Monteiro, Guilherme Flach, Marcelo O. Johann, José Luís Almada Güntzel:
An analytical timing-driven algorithm for detailed placement. LASCAS 2015: 1-4 - [c31]Roger Caputo-Llanos
Energy-efficient Level Shifter topology. PATMOS 2015: 148-151 - [c30]Julia Casarin Puget, Guilherme Flach, Marcelo O. Johann, Ricardo Augusto da Luz Reis
Jezz: An Effective Legalization Algorithm for Minimum Displacement. SBCCI 2015: 19:1-19:5 - [c29]Guilherme Flach, Jucemar Monteiro, Mateus Fogaça
An Incremental Timing-Driven flow using quadratic formulation for detailed placement. VLSI-SoC 2015: 1-6 - [p2]Damián Keller
Interaction Aesthetics and Ubiquitous Music. Creativity in the Digital Age 2015: 91-105 - 2014
- [j5]Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 546-557 (2014) - [j4]Vinicius S. Livramento, Chrystian Guth, José Luís Almada Güntzel, Marcelo O. Johann:
A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation. ACM Trans. Design Autom. Electr. Syst. 19(4): 40:1-40:25 (2014) - [c28]Damián Keller, Nuno Otero
Relational Properties in Interaction Aesthetics: The Ubiquitous Music Turn. EVA 2014 - [c27]Damián Keller, Joseph Timoney, Leandro Lesqueves Costalonga, Ariadna Capasso, Patricia Tinajero, Victor Lazzarini, Marcelo Soares Pimenta, Maria Helena de Lima, Marcelo O. Johann:
Ecologically grounded multimodal design: The Palafito 1.0 study. ICMC 2014 - [p1]Lucas Fialho Zawacki, Marcelo de Oliveira Johann:
Analogue Audio Recording Using Remote Servers. Ubiquitous Music 2014: 83-107 - 2013
- [c26]Vinicius S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann:
Fast and efficient lagrangian relaxation-based discrete gate sizing. DATE 2013: 1855-1860 - [c25]Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis
Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing. ISCAS 2013: 2549-2552 - [c24]Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis
Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities. ISVLSI 2013: 84-89 - [c23]Marcelo O. Johann:
Recent advances and challenges in physical design automation. ISVLSI 2013: 223 - 2012
- [j3]Renato Fernandes Hentschke, Marcelo O. Johann, Ricardo Reis:
Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias. RITA 19(1): 28-45 (2012) - [c22]Vinicius dos S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann:
Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization. ICECS 2012: 468-471 - [c21]Marcelo O. Johann, Lucas Fialho Zawacki:
A System for recording analog synthesizers with the Web. ICMC 2012 - 2011
- [c20]Guilherme Flach, Marcelo O. Johann, Ricardo Reis
Quadratic placement with single-iteration linear system solver. SBCCI 2011: 109-112 - [e1]Jürgen Becker, Marcelo O. Johann, Ricardo Reis
VLSI-SoC: Technologies for Systems Integration - 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, Brazil, October 12-14, 2009, Revised Selected Papers. IFIP Advances in Information and Communication Technology 360, Springer 2011, ISBN 978-3-642-23119-3 [contents] - 2010
- [j2]Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis:
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits. CLEI Electron. J. 13(3) (2010) - [c19]Glauco Borges Valim dos Santos, Tiago Reimann, Marcelo O. Johann, Ricardo Reis
The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms. ICCD 2010: 195-202 - [c18]Felipe Pinto, Lucas Cavalheiro, Marcelo O. Johann, Ricardo Reis
Logical Core Algorithm: Improving Global Placement. ISVLSI 2010: 69-73 - [c17]Guilherme Flach, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis
A Mesh-Buffer Displacement Optimization Strategy. ISVLSI 2010: 282-287
2000 – 2009
- 2009
- [j1]Renato Fernandes Hentschke, Jagannathan Narasimhan, Marcelo O. Johann, Ricardo Reis:
Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1073-1086 (2009) - [c16]Glauco B. V. dos Santos, Tiago Reimann, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis:
On the accuracy of Elmore-based Delay Models. ICECS 2009: 447-450 - [c15]Sandro Sawicki
A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits. ICECS 2009: 852-855 - 2007
- [c14]Renato Fernandes Hentschke, Jaganathan Narasimham, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
Maze routing steiner trees with effective critical sink optimization. ISPD 2007: 135-142 - [c13]Guilherme Flach, Marcelo O. Johann, Renato Fernandes Hentschke, Ricardo Reis:
Cell placement on graphics processing units. SBCCI 2007: 87-92 - 2006
- [c12]Sandro Sawicki
Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits. ICECS 2006: 399-402 - [c11]Glauco Borges Valim dos Santos, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis:
Channel based routing in channel-less circuits. ISCAS 2006 - [c10]Renato Fernandes Hentschke, Sandro Sawicki
An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias. VLSI-SoC 2006: 128-133 - [c9]Renato Fernandes Hentschke, Sandro Sawicki
A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits. VLSI-SoC (Selected Papers) 2006: 259-279 - 2005
- [c8]Renato Fernandes Hentschke, Marcelo O. Johann, Ricardo Reis:
Blue Macaw: A Didactic Placement Tool Using Simulated Annealing. EDUTECH 2005: 37-47 - 2004
- [c7]Alex Panato, Sandro V. Silva, Flávio Rech Wagner, Marcelo O. Johann, Ricardo Reis, Sergio Bampi
Design of Very Deep Pipelined Multipliers for FPGAs. DATE 2004: 52-57 - 2003
- [c6]Renato Fernandes Hentschke, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis:
A study on the performance of fast initial placement algorithms. VLSI-SOC 2003: 204- - 2002
- [c5]Marcelo de Oliveira Johann, Glauco Borges Valim dos Santos, Ricardo Augusto da Luz Reis:
A LEGAL Algorithm Following Global Routing. SBCCI 2002: 271-276 - 2001
- [c4]Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis:
LEGAL: An Algorithm for Simultaneous Net Routing. SBCCI 2001: 180-185 - 2000
- [c3]Marcelo O. Johann, Ricardo Reis:
Net by Net Routing with a New Path Search Algorithm. SBCCI 2000: 144-149 - [c2]Marcelo O. Johann, Andrew E. Caldwell, Ricardo Augusto da Luz Reis, Andrew B. Kahng:
Admissibility Proofs for the LCS* Algorithm. IBERAMIA-SBIA 2000: 236-244
1990 – 1999
- 1999
- [c1]Fernanda Lima, Marcelo O. Johann, José Luís Almada Güntzel, Eduardo D'Avila, Luigi Carro, Ricardo Augusto da Luz Reis:
Designing a Mask Programmable Matrix for Sequential Circuits. VLSI 1999: 439-446
Coauthor Index
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