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Sudipta Bhawmik
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2010 – 2019
- 2015
- [j12]Ran Wang, Krishnendu Chakrabarty
, Sudipta Bhawmik:
Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(1): 136-149 (2015) - [j11]Ran Wang, Krishnendu Chakrabarty
Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC. ACM Trans. Design Autom. Electr. Syst. 20(4): 58:1-58:24 (2015) - 2014
- [c18]Ran Wang, Krishnendu Chakrabarty
Built-in self-test for interposer-based 2.5D ICs. ICCD 2014: 181-188 - [c17]Ran Wang, Krishnendu Chakrabarty
At-speed interconnect testing and test-path optimization for 2.5D ICs. VTS 2014: 1-6 - 2013
- [c16]Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen
Using 3D-COSTAR for 2.5D test cost optimization. 3DIC 2013: 1-8 - [c15]Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen
Impact of mid-bond testing in 3D stacked ICs. DFTS 2013: 178-183
2000 – 2009
- 2003
- [c14]Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod:
The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data. ITC 2003: 998-1007 - 2002
- [j10]Subhayu Basu, Indranil Sengupta, Dipanwita Roy Chowdhury, Sudipta Bhawmik:
An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch. J. Electron. Test. 18(4-5): 475-485 (2002) - [c13]Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik:
Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch. ASP-DAC/VLSI Design 2002: 598-603 - 2001
- [c12]Sudipta Bhawmik:
Introduction to SystemC. VLSI Design 2001: 7-8 - 2000
- [j9]Indradeep Ghosh
A BIST scheme for RTL circuits based on symbolic testabilityanalysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1): 111-128 (2000) - [j8]Huan-Chih Tsai, Kwang-Ting Cheng
On improving test quality of scan-based BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 928-938 (2000) - [c11]Frank P. Higgins, Sudipta Bhawmik:
Core Based ASIC Design. VLSI Design 2000: 10
1990 – 1999
- 1999
- [c10]Huan-Chih Tsai, Kwang-Ting Cheng
Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme. DAC 1999: 748-753 - [c9]Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik:
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing. VLSI Design 1999: 416-422 - 1998
- [j7]Huan-Chih Tsai, Kwang-Ting Cheng
Efficient test-point selection for scan-based BIST. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 667-676 (1998) - [c8]Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik:
A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. DAC 1998: 554-559 - [c7]Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik:
A BIST scheme for the detection of path-delay faults. ITC 1998: 422-431 - [c6]Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng:
An almost full-scan BIST solution-higher fault coverage and shorter test application time. ITC 1998: 1065-1073 - 1997
- [c5]Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik:
A Hybrid Algorithm for Test Point Selection for Scan-Based BIST. DAC 1997: 478-483 - [c4]Sudipta Bhawmik, Indradeep Ghosh:
A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits. VLSI Design 1997: 284-288 - 1995
- [j6]Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik:
Integration of partial scan and built-in self-test. J. Electron. Test. 7(1-2): 125-137 (1995) - 1993
- [c3]Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik:
PSBIST: A Partial-Scan Based Built-In Self-Test Scheme. ITC 1993: 507-516 - 1991
- [c2]Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin:
Enhanced Controllability for IDDQ Test Sets Using Partial Scan. DAC 1991: 278-281
1980 – 1989
- 1989
- [j5]Sudipta Bhawmik, Parimal Palchaudhuri:
DFT Expert: designing testable VLSI circuits. IEEE Des. Test 6(5): 8-19 (1989) - [j4]Sudipta Bhawmik, V. K. Narang, Parimal Pal Chaudhuri:
Selecting test methodologies for PLAs and random logic modules in VLSI circuits - an expert systems approach. Integr. 7(3): 267-281 (1989) - [j3]Anurag Acharya, Sudipta Bhawmik, C. R. K. Prasad, Parimal Palchaudhuri:
KIDLAN: A hardware description language. Microprocessing and Microprogramming 26(1): 1-13 (1989) - [j2]Sudipta Bhawmik, Parimal Pal Chaudhuri:
Expert system to configure global design for testability structure in a VLSI circuit. Microprocess. Microsystems 13(7): 462-472 (1989) - [j1]Prasad R. Chalasani, Sudipta Bhawmik, Anurag Acharya, Parimal Palchaudhuri:
Design of Testable VLSI Circuits with Minumum Area Overhead. IEEE Trans. Computers 38(10): 1460-1462 (1989) - 1988
- [c1]Sudipta Bhawmik, Parimal Pal Chaudhuri:
DFTEXPERT: An Expert System for Design of Testable VLSI Circuits. IEA/AIE (Vol. 1) 1988: 388-396
Coauthor Index
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