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Daniel Palmer Dabbelt
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2020 – today
- 2020
- [j2]John Charles Wright
, Colin Schmidt, Ben Keller
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2721-2725 (2020)
2010 – 2019
- 2017
- [j1]Ben Keller
A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI. IEEE J. Solid State Circuits 52(7): 1863-1875 (2017) - [c4]Angie Wang, Brian C. Richards, Daniel Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn
A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET. A-SSCC 2017: 305-308 - [c3]Jonathan Bachrach, Albert Magyar, Daniel Palmer Dabbelt, Patrick Li, Richard Lin, Krste Asanovic:
Cyclist: Accelerating hardware development. ICCAD 2017: 1011-1018 - 2016
- [c2]Ben Keller, Martin Cochet, Brian Zimmer, Yunsup Lee, Milovan Blagojevic, Jaehwa Kwak, Alberto Puggelli, Stevo Bailey, Pi-Feng Chiu, Daniel Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanovic, Borivoje Nikolic
Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC. ESSCIRC 2016: 269-272 - [c1]Daniel Palmer Dabbelt, Colin Schmidt, Eric Love, Howard Mao, Sagar Karandikar, Krste Asanovic:
Vector Processors for Energy-Efficient Embedded Systems. MES@ISCA 2016: 10-16 - [i1]Christopher Celio, Daniel Palmer Dabbelt, David A. Patterson, Krste Asanovic:
The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V. CoRR abs/1607.02318 (2016)
Coauthor Index
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