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Shanshi Huang
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2020 – today
- 2024
- [i4]Cong Wang, Zeming Chen, Shanshi Huang:
MICSim: A Modular Simulator for Mixed-signal Compute-in-Memory based AI Accelerator. CoRR abs/2409.14838 (2024) - [i3]Xipeng Lin, Shanshi Huang, Hongwu Jiang:
Voxel-CIM: An Efficient Compute-in-Memory Accelerator for Voxel-based Point Cloud Neural Networks. CoRR abs/2409.19077 (2024) - 2023
- [b1]Shanshi Huang:
Reliability and Security of Compute-In-Memory Based Deep Neural Network Accelerators. Georgia Institute of Technology, Atlanta, GA, USA, 2023 - [j10]Hongwu Jiang
, Shanshi Huang
ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 353-363 (2023) - [j9]Shanshi Huang
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators. ACM Trans. Design Autom. Electr. Syst. 28(3): 34:1-34:23 (2023) - 2022
- [j8]Hongwu Jiang
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators. IEEE Des. Test 39(2): 48-55 (2022) - [j7]Jian-Wei Su
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. IEEE J. Solid State Circuits 57(2): 609-624 (2022) - [j6]Wantong Li
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References. IEEE J. Solid State Circuits 57(9): 2868-2877 (2022) - [j5]Shanshi Huang
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices. ACM Trans. Design Autom. Electr. Syst. 27(4): 37:1-37:19 (2022) - [c14]Hongwu Jiang, Wantong Li, Shanshi Huang, Shimeng Yu
A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays. VLSI Technology and Circuits 2022: 266-267 - 2021
- [j4]Xiaochen Peng
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2306-2319 (2021) - [j3]Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu
A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference. ACM Trans. Design Autom. Electr. Syst. 26(6): 45:1-45:18 (2021) - [j2]Shanshi Huang
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2027-2039 (2021) - [c13]Wantong Li
Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security. CICC 2021: 1-2 - [c12]Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu
A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator. DATE 2021: 932-937 - [c11]Wantong Li
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References. ESSCIRC 2021: 79-82 - [c10]Wantong Li
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References. ESSDERC 2021: 79-82 - [c9]Shanshi Huang, Xiaochen Peng, Hongwu Jiang, Yandong Luo, Shimeng Yu
Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning. ISCAS 2021: 1-5 - [c8]Shanshi Huang, Hongwu Jiang, Shimeng Yu
Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune. NVMSA 2021: 1-6 - [i2]Shanshi Huang, Hongwu Jiang, Shimeng Yu:
Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune. CoRR abs/2104.06377 (2021) - 2020
- [j1]Hongwu Jiang
CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays. IEEE Trans. Computers 69(7): 944-954 (2020) - [c7]Shimeng Yu
Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects. CICC 2020: 1-4 - [c6]Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu
A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. DAC 2020: 1-6 - [c5]Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu
Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories. DATE 2020: 1025-1030 - [c4]Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li
XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption. ICCAD 2020: 77:1-77:6 - [c3]Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Shimeng Yu:
MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture. ISCAS 2020: 1-5 - [c2]Jian-Wei Su
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. ISSCC 2020: 240-242 - [i1]Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu:
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training. CoRR abs/2003.06471 (2020)
2010 – 2019
- 2019
- [c1]Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu
CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training. MEMSYS 2019: 490-496
Coauthor Index
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