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Leneesh Raghavan
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2010 – 2019
- 2019
- [j3]Yongjia Li
, Mario Motz, Leneesh Raghavan:
A Fast T&H Overcurrent Detector for a Spinning Hall Current Sensor With Ping-Pong and Chopping Techniques. IEEE J. Solid State Circuits 54(7): 1852-1861 (2019) - 2018
- [c4]Yongjia Li, Mario Motz, Leneesh Raghavan:
A Signal and Offset T&H Frontend for Spinning Hall Sensors with Ping-Pong and Chopping Techniques. ESSCIRC 2018: 338-341 - 2012
- [j2]Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan:
A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. IEEE J. Solid State Circuits 47(4): 911-925 (2012) - [j1]Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan:
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. IEEE J. Solid State Circuits 47(4): 926-937 (2012) - 2010
- [c3]Leneesh Raghavan, Ting Wu:
Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link. VLSI Design 2010: 270-275
2000 – 2009
- 2009
- [c2]H. Md. Shuaeb Fazeel, Leneesh Raghavan, Chandrasekaran Srinivasaraman, Manish Jain:
Reduction of Current Mismatch in PLL Charge Pump. ISVLSI 2009: 7-12 - [c1]Vijay Khawshe, Kapil Vyas, Renu Rangnekar, Prateek Goyal, Vijay Krishna, Kashinath Prabhu, Pravin Kumar Venkatesan, Leneesh Raghavan, Rajkumar Palwai, M. Thrivikraman, Kunal Desai, Abhijit Abhyankar:
A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link. VLSI Design 2009: 373-378
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