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Keerthikumara Devarajegowda
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2020 – today
- 2024
- [c28]Johannes Müller, Anna Lena Duque Antón
, Lucas Deutschmann
MCU-Wide Timing Side Channels and Their Detection. DAC 2024: 292:1-292:6 - 2023
- [c27]Saranyu Chattopadhyay
G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators. DAC 2023: 1-6 - [c26]Endri Kaja, Nicolas Gerlin, Robert Kunzelmann
Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation. MCSoC 2023: 508-515 - 2022
- [c25]Endri Kaja, Nicolas Gerlin, Monideep Bora
MetaFS: Model-driven Fault Simulation Framework. DFT 2022: 1-4 - [c24]Sebastian Prebeck, Sathya Ashok, Mounika Vaddeboina, Keerthikumara Devarajegowda, Wolfgang Ecker:
A Scalable, Configurable and Programmable Vector Dot-Product Unit for Edge AI. MBMV 2022: 1-9 - [c23]Nicolas Gerlin, Endri Kaja, Monideep Bora
Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection. VLSI-SoC 2022: 1-6 - [c22]Endri Kaja, Nicolas Gerlin, Monideep Bora
Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation. VLSI-SoC 2022: 1-6 - [i2]Endri Kaja, Nicolas Gerlin, Luis Rivas, Monideep Bora
MetFI: Model-driven Fault Simulation Framework. CoRR abs/2204.13183 (2022) - 2021
- [b1]Keerthikumara Devarajegowda:
Model-based Generation of Assertions for Pre-silicon Verification. Kaiserslautern University of Technology, Germany, 2021 - [c21]Keerthikumara Devarajegowda, Endri Kaja, Sebastian Siegfried Prebeck, Wolfgang Ecker:
ISA Modeling with Trace Notation for Context Free Property Generation. DAC 2021: 619-624 - [c20]Endri Kaja, Nicolas Gerlin, Mounika Vaddeboina, Luis Rivas, Sebastian Siegfried Prebeck, Zhao Han, Keerthikumara Devarajegowda, Wolfgang Ecker:
Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models. DFT 2021: 1-6 - [c19]Zhao Han, Shahzaib Qazi, Michael Werner, Keerthikumara Devarajegowda, Wolfgang Ecker:
On Self-Verifying DSL Generation for Embedded Systems Automation. MBMV 2021: 1-7 - [c18]Endri Kaja, Nicolas Ojeda Leon, Michael Werner, Bogdan-Andrei Tabacaru, Keerthikumara Devarajegowda, Wolfgang Ecker:
Extending Verilator to Enable Fault Simulation. MBMV 2021: 1-6 - [c17]Zhao Han, Deyan Wang, Gabriel Rutsch, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera
Aspect-Oriented Design Automation with Model Transformation. VLSI-SoC 2021: 1-6 - [c16]Zhao Han, Gabriel Rutsch, Deyan Wang, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera
Transformative Hardware Design Following the Model-Driven Architecture Vision. VLSI-SoC (Selected Papers) 2021: 49-70 - 2020
- [j2]Lorenzo Servadei
Accurate Cost Estimation of Memory Systems Utilizing Machine Learning and Solutions from Computer Vision for Design Automation. IEEE Trans. Computers 69(6): 856-867 (2020) - [c15]Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, Wolfgang Kunz:
Gap-free Processor Verification by S2QED and Property Generation. DATE 2020: 526-531 - [c14]Lorenzo Servadei, Edoardo Mosca, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker, Robert Wille:
Cost Estimation for Configurable Model-Driven SoC Designs Using Machine Learning. ACM Great Lakes Symposium on VLSI 2020: 405-410
2010 – 2019
- 2019
- [j1]Lorenzo Servadei, Elena Zennaro, Tobias Fritz, Keerthikumara Devarajegowda, Wolfgang Ecker, Robert Wille:
Using Machine Learning for predicting area and Firmware metrics of hardware designs from abstract specifications. Microprocess. Microsystems 71 (2019) - [c13]Michael Werner, Keerthikumara Devarajegowda, Moomen Chaari, Wolfgang Ecker:
Increasing Soft Error Resilience by Software Transformation. DAC 2019: 199 - [c12]Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. DATE 2019: 1000-1005 - [c11]Lorenzo Servadei, Elena Zennaro, Keerthikumara Devarajegowda, Martin Manzinger, Wolfgang Ecker, Robert Wille:
Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision. DATE 2019: 1277-1280 - [c10]Wolfgang Ecker, Keerthikumara Devarajegowda, Michael Werner, Zhao Han, Lorenzo Servadei:
Embedded Systems' Automation following OMG's Model Driven Architecture Vision. DATE 2019: 1301-1306 - [c9]Lorenzo Servadei, Zhao Han, Michael Werner, Wolfgang Ecker, Keerthikumara Devarajegowda:
Formal Verification Methodology in an Industrial Setup. DSD 2019: 610-614 - [c8]Keerthikumara Devarajegowda, Wolfgang Ecker, Wolfgang Kunz:
How to Keep 4-Eyes Principle in a Design and Property Generation Flow. MBMV 2019: 1-6 - [c7]Zhao Han, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker:
Towards a Python-Based One Language Ecosystem for Embedded Systems Automation. NORCAS 2019: 1-7 - [i1]Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra:
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. CoRR abs/1902.01494 (2019) - 2018
- [c6]Elena Zennaro, Lorenzo Servadei, Keerthikumara Devarajegowda, Wolfgang Ecker:
A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications. DSD 2018: 413-420 - [c5]Lorenzo Servadei, Elena Zennaro, Keerthikumara Devarajegowda, Wolfgang Ecker, Robert Wille:
Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning. CIMA@ICTAI 2018: 14-27 - [c4]Keerthikumara Devarajegowda, Wolfgang Ecker:
Meta-model Based Automation of Properties for Pre-Silicon Verification. VLSI-SoC 2018: 231-236 - 2017
- [c3]Keerthikumara Devarajegowda, Wolfgang Ecker:
On generation of properties from specification. HLDVT 2017: 95-98 - [c2]Keerthikumara Devarajegowda, Johannes Schreiner, Rainer Findenig, Wolfgang Ecker:
Python based framework for HDSLs with an underlying formal semantics: (Invited paper). ICCAD 2017: 1019-1025 - [c1]Daniel Mueller-Gritschneder
The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. RSP 2017: 79-84
Coauthor Index
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last updated on 2024-12-02 21:26 CET by the dblp team
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