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Noboru Sakimura
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2010 – 2019
- 2016
- [j14]Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu:
Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory. J. Multiple Valued Log. Soft Comput. 26(1-2): 125-140 (2016) - 2015
- [j13]Masanori Natsui
, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits 50(2): 476-489 (2015) - 2014
- [j12]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross:
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(4): 460-474 (2014) - [j11]Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express 11(10): 20140297 (2014) - [j10]Daisuke Suzuki, Noboru Sakimura, Masanori Natsui
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express 11(13): 20140296 (2014) - [c9]Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. ISCAS 2014: 1588-1591 - [c8]Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu:
Soft-Delay-Error Evaluation in Content-Addressable Memory. ISMVL 2014: 220-225 - [c7]Noboru Sakimura, Yukihide Tsuji
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. ISSCC 2014: 184-185 - 2013
- [j9]Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi:
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. Inf. Media Technol. 8(2): 262-269 (2013) - [j8]Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi:
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. IPSJ Trans. Syst. LSI Des. Methodol. 6: 52-59 (2013) - [c6]Masanori Natsui
MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. ISCAS 2013: 105-109 - [c5]Masanori Natsui
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC 2013: 194-195 - 2012
- [j7]Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi:
A non-volatile reconfigurable offloader for wireless sensor nodes. SIGARCH Comput. Archit. News 40(5): 87-92 (2012) - [c4]Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji
High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS 2012: 1971-1974 - 2011
- [c3]Makoto Miyamura, Shogo Nakaya, Munehiro Tada
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS. ISSCC 2011: 228-229
2000 – 2009
- 2009
- [j6]Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai:
Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros. IEICE Trans. Electron. 92-C(4): 417-422 (2009) - [j5]Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai:
Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs. IEEE J. Solid State Circuits 44(8): 2244-2250 (2009) - [c2]Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito, Yuichi Ito, Sadahiko Miura, Yuko Kato, Kaoru Mori, Yasuaki Ozaki, Yosuke Kobayashi, Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Katsumi Suemitsu, Shunsuke Fukami
A 90nm 12ns 32Mb 2T1MTJ MRAM. ISSCC 2009: 462-463 - 2008
- [c1]Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai:
Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs. CICC 2008: 355-358 - 2007
- [j4]Takeshi Honda, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai, Hiromitsu Hada, Shuichi Tahara:
Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode. IEICE Trans. Electron. 90-C(2): 531-535 (2007) - [j3]Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Shuichi Tahara, Naoki Kasai:
MRAM Applications Using Unlimited Write Endurance. IEICE Trans. Electron. 90-C(10): 1936-1940 (2007) - [j2]Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo
MRAM Cell Technology for Over 500-MHz SoC. IEEE J. Solid State Circuits 42(4): 830-838 (2007) - [j1]Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo
A 16-Mb Toggle MRAM With Burst Modes. IEEE J. Solid State Circuits 42(11): 2378-2385 (2007)
Coauthor Index
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