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Michael Adler
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2020 – today
- 2022
- [e2]Michael Adler, Paolo Ienne:
FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022. ACM 2022, ISBN 978-1-4503-9149-8 [contents] - 2021
- [e1]Lesley Shannon, Michael Adler:
FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28 - March 2, 2021. ACM 2021, ISBN 978-1-4503-8218-2 [contents] - 2020
- [j5]Michele Schirru, Michael Adler:
An Ultrasonic Rheometer to Measure Gas Absorption in Ionic Liquids: Design, Calibration and Testing. Sensors 20(12): 3544 (2020)
2010 – 2019
- 2018
- [c16]Samuel Levin, May Yuan, Michael Adler:
Thermographic Quantification for Archaeological Prospection at Picuris Pueblo, New Mexico. DigitalHERITAGE/VSMM 2018: 1-8 - 2017
- [j4]Hsin-Jung Yang
, Kermin Fleming, Felix Winterstein, Michael Adler, Joel S. Emer:
(FPL 2015) Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies. ACM Trans. Reconfigurable Technol. Syst. 10(2): 13:1-13:23 (2017) - [c15]Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Annie I. Chen, Michael Adler, Joel S. Emer:
Automatic Construction of Program-Optimized FPGA Memory Networks. FPGA 2017: 125-134 - 2016
- [c14]Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer:
LMC: Automatic Resource-Aware Program-Optimized Memory Partitioning. FPGA 2016: 128-137 - [p1]Kermin Fleming, Michael Adler:
The LEAP FPGA Operating System. FPGAs for Software Programmers 2016: 245-258 - 2015
- [j3]Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer:
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. ACM Trans. Comput. Syst. 33(3): 10:1-10:32 (2015) - [c13]John Lockwood, Michael Adler, Dan Mansur, Derek Chiou, Mike Strickland, Jason Cong, Steve Teig:
Growing a Healthy FPGA Ecosystem. FPGA 2015: 160 - [c12]Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer:
Scavenger: Automating the construction of application-optimized memory hierarchies. FPL 2015: 1-8 - 2014
- [j2]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Efficient Spatial Processing Element Control via Triggered Instructions. IEEE Micro 34(3): 120-137 (2014) - [c11]Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer:
LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories. FCCM 2014: 117-124 - [c10]Kermin Fleming, Hsin-Jung Yang, Michael Adler, Joel S. Emer:
The LEAP FPGA operating system. FPL 2014: 1-8 - 2013
- [c9]Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer:
Optimizing under abstraction: Using prefetching to improve FPGA performance. FPL 2013: 1-8 - [c8]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Triggered instructions: a control paradigm for spatially-programmed architectures. ISCA 2013: 142-153 - 2012
- [c7]Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer:
Leveraging latency-insensitivity to ease multiple FPGA design. FPGA 2012: 175-184 - [c6]Sang Woo Jun, Kermin Fleming, Michael Adler, Joel S. Emer:
ZIP-IO: Architecture for application-specific compression of Big Data. FPT 2012: 343-351 - 2011
- [c5]Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer:
Leap scratchpads: automatic memory and cache management for reconfigurable logic. FPGA 2011: 25-28 - [c4]Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer:
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. HPCA 2011: 406-417
2000 – 2009
- 2009
- [j1]Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer:
A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(3): 16:1-16:26 (2009) - [c3]Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer:
Soft connections: addressing the hardware-design modularity problem. DAC 2009: 276-281 - 2008
- [c2]Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer:
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. FPGA 2008: 87-96 - [c1]Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer:
Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. ISPASS 2008: 1-10
Coauthor Index
aka: Kermin Elliott Fleming
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