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Hong-Ru Chou
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2010 – 2019
- 2019
- [j6]Xin-Yu Shih
, Hong-Ru Chou:
Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding. Integr. 64: 40-49 (2019) - 2018
- [j5]Xin-Yu Shih
Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems. ICT Express 4(3): 144-148 (2018) - [j4]Xin-Yu Shih
VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system. Integr. 62: 292-300 (2018) - [j3]Xin-Yu Shih
VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 118-129 (2018) - [j2]Xin-Yu Shih
Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3942-3955 (2018) - 2017
- [j1]Xin-Yu Shih
48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(6): 1456-1467 (2017) - [c3]Xin-Yu Shih
A 2-D grouping FIFO based hardware architecture for supporting 36-mode hybrid-radix FFT design in 3GPP-LTE systems. GCCE 2017: 1-2 - [c2]Xin-Yu Shih
Reconfigurable hardware design of low-area-cost computing kernel engine for different radixes of single-path delay feedback FFT systems. ICCE 2017: 418-419 - 2016
- [c1]Xin-Yu Shih
Reconfigurable VLSI design of processing kernel for multiple-radix single-path delay feedback FFT systems. GCCE 2016: 1-2
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