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César Torres-Huitzil
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2020 – today
- 2021
- [j32]Rafael Pérez-Torres, César Torres-Huitzil, Thuy Truong, Donagh Buckley, Cormac J. Sreenan:
Using Context-Awareness for Storage Services in Edge Computing. IT Prof. 23(2): 50-57 (2021) - 2020
- [j31]Marco Aurelio Nuño-Maganda
, César Torres-Huitzil, Yahir Hernandez-Mier
Smartphone-Based Remote Monitoring Tool for e-Learning. IEEE Access 8: 121409-121423 (2020) - [j30]Moisés Arredondo-Velázquez
A streaming architecture for Convolutional Neural Networks based on layer operations chaining. J. Real Time Image Process. 17(5): 1715-1733 (2020) - [j29]Bernard Girau, César Torres-Huitzil
Fault tolerance of self-organizing maps. Neural Comput. Appl. 32(24): 17977-17993 (2020)
2010 – 2019
- 2019
- [j28]Moisés Arredondo-Velázquez
A streaming accelerator of Convolutional Neural Networks for resource-limited applications. IEICE Electron. Express 16(23): 20190633 (2019) - [j27]Rafael Pérez-Torres
A Cognitive-Inspired Event-Based Control for Power-Aware Human Mobility Analysis in IoT Devices. Sensors 19(4): 832 (2019) - [j26]Rafael Pérez-Torres
A Spatio-Temporal Approach to Individual Mobility Modeling in On-Device Cognitive Computing Platforms. Sensors 19(18): 3949 (2019) - 2018
- [j25]Josue Reyes-Garcia
Evaluation of the Impact of Data Uncertainty on the Prediction of Physiological Patient Deterioration. IEEE Access 6: 38595-38606 (2018) - [j24]Rafael Pérez-Torres
An On-Device Cognitive Dynamic Systems Inspired Sensing Framework for the IoT. IEEE Commun. Mag. 56(9): 154-161 (2018) - [j23]Marco Aurelio Nuño-Maganda
On-Device Learning of Indoor Location for WiFi Fingerprint Approach. Sensors 18(7): 2202 (2018) - 2017
- [j22]César Torres-Huitzil
Fault and Error Tolerance in Neural Networks: A Review. IEEE Access 5: 17322-17341 (2017) - [c42]Bernard Girau, César Torres-Huitzil:
Optimal weight storage improves fault tolerance of SOMs. ReConFig 2017: 1-6 - [c41]César Torres-Huitzil, Bernard Girau:
Fault tolerance in neural networks: Neural design and hardware implementation. ReConFig 2017: 1-6 - [c40]César Torres-Huitzil, Oleksandr V. Popovych, Bernard Girau:
Fault tolerance of self organizing maps. WSOM 2017: 13-20 - 2016
- [j21]César Torres-Huitzil:
FPGA-based fast computation of gray-level morphological granulometries. J. Real Time Image Process. 11(3): 547-557 (2016) - [j20]Rafael Pérez-Torres, César Torres-Huitzil, Hiram Galeana-Zapién:
Power management techniques in smartphone-based mobility sensing systems: A survey. Pervasive Mob. Comput. 31: 1-21 (2016) - [j19]Rafael Pérez-Torres, César Torres-Huitzil, Hiram Galeana-Zapién:
Full On-Device Stay Points Detection in Smartphones for Location-Based Mobile Applications. Sensors 16(10): 1693 (2016) - [c39]Benoît Chappet de Vangel, César Torres-Huitzil, Bernard Girau:
Event based visual attention with dynamic neural field on FPGA. ICDSC 2016: 142-147 - 2015
- [j18]Horacio Rostro-González
A CPG system based on spiking neurons for hexapod robot locomotion. Neurocomputing 170: 47-54 (2015) - [j17]Jose Hugo Barron-Zambrano
Perception-driven adaptive CPG-based locomotion for hexapod robots. Neurocomputing 170: 63-78 (2015) - [j16]Benoit Chappet de Vangel, César Torres-Huitzil, Bernard Girau:
Randomly Spiking Dynamic Neural Fields. ACM J. Emerg. Technol. Comput. Syst. 11(4): 37:1-37:26 (2015) - [j15]Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido:
Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs. Microprocess. Microsystems 39(7): 576-588 (2015) - [c38]Benoit Chappet de Vangel, César Torres-Huitzil, Bernard Girau:
Stochastic and asynchronous spiking dynamic neural fields. IJCNN 2015: 1-8 - [c37]César Torres-Huitzil, Marco Aurelio Nuño-Maganda
Robust smartphone-based human activity recognition using a tri-axial accelerometer. LASCAS 2015: 1-4 - 2014
- [j14]César Torres-Huitzil:
Fast hardware architecture for grey-level image morphology with flat structuring elements. IET Image Process. 8(2): 112-121 (2014) - [j13]Hiram Galeana-Zapién, César Torres-Huitzil, Javier Rubio-Loyola:
Mobile Phone Middleware Architecture for Energy and Context Awareness in Location-Based Services. Sensors 14(12): 23673-23696 (2014) - [j12]César Torres-Huitzil, Marco Aurelio Nuño-Maganda:
Areatime Efficient Implementation of Local Adaptive Image Thresholding in Reconfigurable Hardware. SIGARCH Comput. Archit. News 42(4): 33-38 (2014) - [c36]Victor Rodríguez-Osoria, Marco Aurelio Nuño-Maganda, Yahir Hernandez-Mier, César Torres-Huitzil:
Embedded Image Processing System for Automatic Page Segmentation of Open Book Images. ISVC (2) 2014: 531-540 - [c35]Marco Aurelio Nuño-Maganda
FPGA-based real-time citrus classification system. LASCAS 2014: 1-4 - [c34]Carlos Andres Lara-Nino
Versatile educational and research robotic platform based on reconfigurable hardware. ReConFig 2014: 1-6 - [c33]Benoit Chappet de Vangel, César Torres-Huitzil, Bernard Girau:
Spiking dynamic neural fields architectures on FPGA. ReConFig 2014: 1-6 - 2013
- [j11]Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos:
On an external memory scheme for processor arrays. IEICE Electron. Express 10(14): 20130324 (2013) - [j10]Jose Hugo Barron-Zambrano
FPGA implementation of a configurable neuromorphic CPG-based locomotion controller. Neural Networks 45: 50-61 (2013) - [c32]César Torres-Huitzil:
Hardware realization of a lightweight 2D cellular automata-based cipher for image encryption. LASCAS 2013: 1-4 - [c31]Lorenzo Antonio Delgado-Guillen, Jose Juan Garcia-Hernandez, César Torres-Huitzil:
Digital watermarking of color images utilizing mobile platforms. MWSCAS 2013: 1363-1366 - [c30]Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos:
Processor arrays generation for matrix algorithms used in embedded platforms. ReConFig 2013: 1-6 - 2012
- [j9]César Torres-Huitzil, Marco Delgadillo-Escobar, Marco Aurelio Nuño-Maganda
Comparison between 2D cellular automata based pseudorandom number generators. IEICE Electron. Express 9(17): 1391-1396 (2012) - [c29]Marco Delgadillo-Escobar, César Torres-Huitzil:
FPGA implementation of Pseudorandom Number Generators with a generic 2-D cellular automata architecture. CONIELECOMP 2012: 138-143 - [c28]Lorenzo Antonio Delgado-Guillen, Jose Juan Garcia-Hernandez, César Torres-Huitzil:
Validating the existence of watermarks on digital images using a mobile phone. ICITST 2012: 51-55 - [c27]Horacio Rostro-González
An FPGA-based approach for parameter estimation in spiking neural networks. ISCAS 2012: 2897-2900 - [c26]Marco Aurelio Nuño-Maganda
A Hardware Architecture for Image Clustering Using Spiking Neural Networks. ISVLSI 2012: 261-266 - [c25]Jose Hugo Barron-Zambrano
Versatile FPGA-based locomotion platform for legged robots. ReConFig 2012: 1-6 - 2011
- [c24]Marco Aurelio Nuño-Maganda
A Hardware Coprocessor Integrated with OpenCV for Edge Detection Using Cellular Neural Networks. ICIG 2011: 957-962 - [c23]Jose Hugo Barron-Zambrano
Two-phase GA parameter tunning method of CPGs for quadruped gaits. IJCNN 2011: 1767-1774 - [c22]Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos:
On a Hybrid and General Control Scheme for Algorithms Represented as a Polytope. IPDPS Workshops 2011: 330-333 - [c21]Jose Hugo Barron-Zambrano
FPGA-based CPG Robot Locomotion Modulation Using a Fuzzy Scheme and Visual Information. ReConFig 2011: 291-296 - 2010
- [j8]Jose Hugo Barron-Zambrano, César Torres-Huitzil, Bernard Girau:
FPGA-based Circuit for Central Pattern Generator in Quadruped Locomotion. Aust. J. Intell. Inf. Process. Syst. 12(2) (2010) - [j7]Marco Aurelio Nuño-Maganda, César Torres-Huitzil:
A temporal coding hardware implementation for spiking neural networks. SIGARCH Comput. Archit. News 38(4): 2-7 (2010) - [c20]Jose Hugo Barron-Zambrano
Hardware Implementation of a CPG-Based Locomotion Control for Quadruped Robots. ICANN (2) 2010: 276-285
2000 – 2009
- 2009
- [j6]Bernard Girau, César Torres-Huitzil, Nikolaos Vlassopoulos, Jose Hugo Barron-Zambrano:
Reaction Diffusion and Chemotaxis for Decentralized Gathering on FPGAs. Int. J. Reconfigurable Comput. 2009: 639249:1-639249:15 (2009) - [c19]Marco Aurelio Nuño-Maganda
Hardware implementation of Spiking Neural Network classifiers based on backpropagation-based learning algorithms. IJCNN 2009: 2294-2301 - [c18]César Torres-Huitzil:
On the Implementation of Central Pattern Generators for Periodic Rhythmic Locomotion. ReConFig 2009: 422-426 - 2008
- [c17]César Torres-Huitzil, Bernard Girau:
Implementation of Central Pattern Generator in an FPGA-Based Embedded System. ICANN (2) 2008: 179-187 - [c16]César Torres-Huitzil, Bernard Girau, Miguel O. Arias-Estrada
Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity. ICANN (2) 2008: 188-197 - [c15]César Torres-Huitzil, Bernard Girau, Amine M. Boumaza, Bruno Scherrer:
Embedded Harmonic Control for Trajectory Planning in Large Environments. ReConFig 2008: 7-12 - [c14]Jose Hugo Barron-Zambrano
Flexible Architecture for Three Classes of Optical Flow Extraction Algorithms. ReConFig 2008: 13-18 - [c13]Bernard Girau, César Torres-Huitzil:
Fast Implementation of a Bio-inspired Model for Decentralized Gathering. ReConFig 2008: 229-234 - 2007
- [j5]Bernard Girau, César Torres-Huitzil:
Massively distributed digital implementation of an integrate-and-fire LEGION network for visual scene segmentation. Neurocomputing 70(7-9): 1186-1197 (2007) - [c12]César Torres-Huitzil, Bernard Girau, Adrien Gauffriau:
Hardware/Software Codesign for Embedded Implementation of Neural Networks. ARC 2007: 167-178 - [c11]Marco Aurelio Nuño-Maganda
High Performance Hardware Implementation of SpikeProp Learning: Potential and Tradeoffs. FPT 2007: 129-136 - 2006
- [c10]Bernard Girau, César Torres-Huitzil:
FPGA implementation of an integrate-and-fire LEGION model for image segmentation. ESANN 2006: 173-178 - [c9]César Torres-Huitzil:
Area-Efficient Implementation of a Pulse-Mode Neuron Model. FPL 2006: 1-4 - [c8]César Torres-Huitzil:
A Bit-Stream Pulse-Based Digital Neuron Model for Neural Networks. ICONIP (3) 2006: 1150-1159 - [e1]René Cumplido-Parra, César Torres-Huitzil, Andrés D. García:
2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006, San Luis Potosi, Mexico, September 20-22, 2006. IEEE Computer Society 2006, ISBN 1-4244-0690-0 [contents] - 2005
- [j4]César Torres-Huitzil, Miguel O. Arias-Estrada
FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing. EURASIP J. Adv. Signal Process. 2005(7): 1024-1034 (2005) - [j3]César Torres-Huitzil, Bernard Girau, Claudio Castellanos Sánchez:
On-chip visual perception of motion: A bio-inspired connectionist model on FPGA. Neural Networks 18(5-6): 557-565 (2005) - [c7]César Torres-Huitzil, Bernard Girau:
FPGA Implementation of an Excitatory and Inhibitory Connectionist Model for Motion Perception. FPT 2005: 259-266 - 2004
- [j2]César Torres-Huitzil, Miguel O. Arias-Estrada
Real-time image processing with a compact FPGA-based systolic architecture. Real Time Imaging 10(3): 177-187 (2004) - [c6]Santos López-Estrada, René Cumplido-Parra, César Torres-Huitzil:
A Hybrid Approach for Target Detection Using CFAR Algorithm and Image Processing. ENC 2004: 108-115 - [c5]César Torres-Huitzil, René Cumplido-Parra, Santos López-Estrada:
Design and Implementation of a CFAR Processor for Target Detection. FPL 2004: 943-947 - 2003
- [c4]César Torres-Huitzil, Miguel O. Arias-Estrada
Configurable Hardware Architecture for Real-Time Window-Based Image Processing. FPL 2003: 1008-1011 - 2002
- [c3]César Torres-Huitzil, Selene Maya-Rueda, Miguel O. Arias-Estrada
A reconfigurable vision system for real-time applications. FPT 2002: 286-289 - 2001
- [j1]Miguel O. Arias-Estrada
Real-time field programmable gate array architecture for computer vision. J. Electronic Imaging 10(1): 289-296 (2001) - 2000
- [c2]César Torres-Huitzil, Miguel O. Arias-Estrada:
An FPGA Architecture for High Speed Edge and Corner Detection. CAMP 2000: 112-116 - [c1]Selene Maya, M. Rocio Reynoso, César Torres-Huitzil, Miguel O. Arias-Estrada:
Compact Spiking Neural Network Implementation in FPGA. FPL 2000: 270-276
Coauthor Index
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