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Zhimin Zhang 0004
Person information
- affiliation: Chinese Academy of Sciences, State Key Laboratory of Computer Architecture, SKLCA, Institute of Computing Technology, Beijing, China
Other persons with the same name
- Zhimin Zhang (aka: Zhi-min Zhang, Zhi-Min Zhang) — disambiguation page
- Zhimin Zhang 0001 — Chinese Academy of Science, Institute of Electronics, Aerospace Information Research Institute, AIRCAS, Beijing, China (and 1 more)
- Zhimin Zhang 0002 — Wayne State University, Department of Mathematics, Detroit, MI, USA (and 1 more)
- Zhimin Zhang 0003
— University of Chinese Academy of Sciences, Beijing, China (and 1 more)
- Zhimin Zhang 0005
- Zhimin Zhang 0006
- Zhimin Zhang 0007
- Zhimin Zhang 0008
- Zhimin Zhang 0009 — Chongqing University, College of Mathematics and Statistics, Department of Statistics and Actuarial Science, China
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2020 – today
- 2024
- [c16]Siyan Chen, Rongliang Fu, Junying Huang, Zhimin Zhang, Xiaochun Ye, Tsung-Yi Ho, Dongrui Fan:
JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. DATE 2024: 1-6 - [i3]Meng Wu, Jingkai Qiu, Mingyu Yan, Wenming Li, Yang Zhang, Zhimin Zhang, Xiaochun Ye, Dongrui Fan:
Accelerating Mini-batch HGNN Training by Reducing CUDA Kernels. CoRR abs/2408.08490 (2024) - 2023
- [j5]Meng Wu
Characterizing and Understanding Defense Methods for GNNs on GPUs. IEEE Comput. Archit. Lett. 22(2): 137-140 (2023) - [j4]Kuozhong Zhang
Design of a Compact Superconducting RSFQ Register File. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4470-4477 (2023) - [c15]Xinda Chen
JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits. ACM Great Lakes Symposium on VLSI 2023: 515-520 - 2021
- [c14]Rongliang Fu
Equivalence Checking for Superconducting RSFQ Logic Circuits. ACM Great Lakes Symposium on VLSI 2021: 51-56 - 2020
- [j3]Mingyu Yan
Characterizing and Understanding GCNs on GPU. IEEE Comput. Archit. Lett. 19(1): 22-25 (2020) - [c13]Rongliang Fu
Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits. ACM Great Lakes Symposium on VLSI 2020: 145-150 - [c12]Mingyu Yan, Lei Deng
HyGCN: A GCN Accelerator with Hybrid Architecture. HPCA 2020: 15-29 - [i2]Mingyu Yan, Lei Deng, Xing Hu, Ling Liang, Yujing Feng, Xiaochun Ye, Zhimin Zhang, Dongrui Fan, Yuan Xie:
HyGCN: A GCN Accelerator with Hybrid Architecture. CoRR abs/2001.02514 (2020) - [i1]Mingyu Yan, Zhaodong Chen, Lei Deng, Xiaochun Ye, Zhimin Zhang, Dongrui Fan, Yuan Xie:
Characterizing and Understanding GCNs on GPU. CoRR abs/2001.10160 (2020)
2010 – 2019
- 2019
- [c11]Kuozhong Zhang
iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack. IOLTS 2019: 287-292 - [c10]Mingyu Yan, Xing Hu, Shuangchen Li, Itir Akgun, Han Li, Xin Ma, Lei Deng
Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators. ISLPED 2019: 1-6 - [c9]Junying Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan
Instruction Vulnerability Test and Code Optimization Against DVFS Attack. ITC-Asia 2019: 49-54 - [c8]Mingyu Yan, Xing Hu, Shuangchen Li, Abanti Basak, Han Li, Xin Ma, Itir Akgun, Yujing Feng, Peng Gu, Lei Deng
Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach. MICRO 2019: 615-628 - 2018
- [j2]Xu Tan, Xiaowei Shen, Xiaochun Ye, Da Wang, Dongrui Fan
A Non-Stop Double Buffering Mechanism for Dataflow Architecture. J. Comput. Sci. Technol. 33(1): 145-157 (2018) - [c7]Wenming Li, Xiaochun Ye, Da Wang, Hao Zhang, Dongdong Wu, Zhimin Zhang, Dongrui Fan
WEAVER: An Energy Efficient, General-Purpose Acceleration Architecture for String Operations in Big Data Applications. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 47-54 - [c6]Shigan Yu, Zhimin Tang, Xiaochun Ye, Zhimin Zhang, Dongrui Fan
High-Performance and Energy-Efficient Fault Tolerance Scheduling Algorithm Based on Improved TMR for Heterogeneous System. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 207-214 - 2017
- [j1]Xiaowei Shen, Xiaochun Ye, Xu Tan, Da Wang, Lunkai Zhang, Wenming Li, Zhimin Zhang, Dongrui Fan
An Efficient Network-on-Chip Router for Dataflow Architecture. J. Comput. Sci. Technol. 32(1): 11-25 (2017) - 2016
- [c5]Xiaowei Shen, Xiaochun Ye, Xu Tan, Da Wang, Zhimin Zhang, Dongrui Fan
POSTER: An Optimization of Dataflow Architectures for Scientific Applications. PACT 2016: 441-442 - [c4]Xiaowei Shen, Xiaochun Ye, Xu Tan, Da Wang, Zhimin Zhang, Zhimin Tang, Dongrui Fan
Memory partition for SIMD in streaming dataflow architectures. IGSC 2016: 1-8 - [c3]Yatao Zhu, Xiaochun Ye, Da Wang, Wenming Li, Yang Zhang, Dongrui Fan
A framework for energy-efficient optimization on multi-cores. IGSC 2016: 1-8 - [c2]Yatao Zhu, Shuai Zhang, Xiaochun Ye, Da Wang, Xu Tan, Dongrui Fan
An energy-efficient bandwidth allocation method for single-chip heterogeneous processor. IGSC 2016: 1-7
2000 – 2009
- 2005
- [c1]Xiaotao Chang, Dongrui Fan, Yinhe Han, Zhimin Zhang:
SoC Leakage Power Reduction Algorithm by Input Vector Control. SoC 2005: 86-89
Coauthor Index
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