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Zhirui Zong
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2020 – today
- 2024
- [j7]Haotian Fu
, Yulong Huang, Tingran Chen, Chenyi Fu
DS-CIM: A 40nm Asynchronous Dual-Spike Driven, MRAM Compute-In-Memory Macro for Spiking Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 71(4): 1638-1650 (2024) - 2023
- [j6]Zhong Gao
A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit. IEEE J. Solid State Circuits 58(6): 1552-1571 (2023) - 2022
- [c3]Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza S. Alavi
A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs. ISSCC 2022: 380-382 - 2021
- [j5]Yiming Yu, Jiahong Zhu, Zhirui Zong
A 21-to-41-GHz High-Gain Low Noise Amplifier With Triple-Coupled Technique for Multiband Wireless Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 1857-1861 (2021)
2010 – 2019
- 2019
- [j4]Yue Chen
A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and Cancellation. IEEE J. Solid State Circuits 54(1): 240-252 (2019) - [j3]Zhirui Zong
A Low-Noise Fractional- ${N}$ Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications. IEEE J. Solid State Circuits 54(3): 755-767 (2019) - [j2]Peng Chen
A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS. IEEE J. Solid State Circuits 54(11): 3075-3085 (2019) - [c2]Feng-Wei Kuo, Zhirui Zong
A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic. ESSCIRC 2019: 53-56 - 2017
- [c1]Peng Chen
A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS. A-SSCC 2017: 93-96 - 2016
- [j1]Zhirui Zong
A 60 GHz Frequency Generator Based on a 20 GHz Oscillator and an Implicit Multiplier. IEEE J. Solid State Circuits 51(5): 1261-1273 (2016)
Coauthor Index
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