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Ming-Hsiu Lee
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2020 – today
- 2024
- [j2]Ming-Hsiu Lee, Jing-Sin Liu
:
Reliable and Accurate Implicit Neural Representation of Multiple Swept Volumes with Application to Safe Human-Robot Interaction. SN Comput. Sci. 5(3): 313 (2024) - [c8]Po-Hao Tseng, Shao-Yu Fang, Yu-Hsuan Lin, Feng-Ming Lee, Jhe-Yi Liao, Yu-Yu Lin, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
3D-NAND based Filtering Cube with High Resolution 2D Query and Tunable Feature Length for Computational SSD. IMW 2024: 1-4 - [c7]Po-Hao Tseng, Yu-Hsuan Lin, Feng-Min Lee, Tian-Cig Bo, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
Reliability Assessment for an In-3D-NAND Approximate Searching Solution. IRPS 2024: 1-6 - [c6]Feng-Min Lee, Po-Hao Tseng, Yu-Yu Lin, Yu-Hsuan Lin, Wei-Lun Weng, Nei-Chih Lin, Po-Jung Sung, Chien-Ting Wu, Chih-Chao Yang, Wen-Fa Wu, Chang-Hong Shen, Tuo-Hung Hou, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs. VLSI Technology and Circuits 2024: 1-2 - [c5]Zefu Zhao, Yu-Rui Chen, Yu-Tsung Liao, Yun-Wen Chen, Wan-Hsuan Hsieh, Jer-Fu Wang, Yu-An Chen, Hao-Yi Lu, Wei-Teng Hsu, Dai-Ying Lee, Ming-Hsiu Lee, C. W. Liu:
Engineering HZO by Flat Amorphous TiN with 0.3nm Roughness Achieving Uniform c-Axis Alignment, Record High Breakdown Field (~10nm HZO), and Record Final 2Pr of 56 μC/cm2 with Endurance > 4E12. VLSI Technology and Circuits 2024: 1-2 - [i1]Hao-Wei Chiang, Chi-Tse Huang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Wu:
Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot Learning. CoRR abs/2409.07832 (2024) - 2023
- [c4]Po-Hao Tseng, Tian-Cig Bo, Yu-Hsuan Lin, Yu-Chao Lin, Jhe-Yi Liao, Feng-Ming Lee, Yu-Yu Lin, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
SLC and MLC In-Memory-Approximate-Search Solutions in Commercial 48-layer and 96-layer 3D-NAND Flash Memories. IMW 2023: 1-4 - 2022
- [c3]Yu-Hsuan Lin, Po-Hao Tseng, Feng-Min Lee, Ming-Hsiu Lee, Chih-Chang Hsieh, Dai-Ying Lee, Keh-Chung Wang, Chih-Yuan Lu:
NOR Flash-based Multilevel In-Memory-Searching Architecture for Approximate Computing. IMW 2022: 1-4 - [c2]Po-Hao Tseng, Yu-Hsuan Lin, Feng-Ming Lee, Tian-Cig Bo, Yung-Chun Li, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
In-Memory Approximate Computing Architecture Based on 3D-NAND Flash Memories. VLSI Technology and Circuits 2022: 270-271
2010 – 2019
- 2017
- [j1]Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew J. BrightSky, SangBum Kim
A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications. IEEE J. Solid State Circuits 52(1): 218-228 (2017) - 2016
- [c1]Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew BrightSky, SangBum Kim, Hsiang-Lam Lung, Chung Lam:
7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications. ISSCC 2016: 134-135
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last updated on 2024-10-18 19:26 CEST by the dblp team
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