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Chiharu Tsuruta
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2010 – 2019
- 2017
- [c5]Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano:
Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA. FPL 2017: 1-4 - [c4]Takahiro Kaneda, Ryotaro Sakai, Naoki Nishikawa, Toshihiro Hanawa
, Chiharu Tsuruta, Hideharu Amano:
Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators. HEART 2017: 9:1-9:6 - 2016
- [c3]Hiroshi Nakahara, Tetsui Ohkubo, Hideki Shimura, Ryotaro Sakai, Chiharu Tsuruta, Takahiro Kaneda, Hideharu Amano:
Trax solver on Zynq using incremental update algorithm. FPT 2016: 323-326 - 2015
- [j1]Chiharu Tsuruta, Yohei Miki
Off-Loading LET Generation to PEACH2: A Switching Hub for High Performance GPU Clusters. SIGARCH Comput. Archit. News 43(4): 3-8 (2015) - [c2]Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa
Reduction calculator in an FPGA based switching Hub for high performance clusters. FPL 2015: 1-4 - [c1]Naru Sugimoto, Takuji Mitsuishi, Takahiro Kaneda, Chiharu Tsuruta, Ryotaro Sakai, Hideki Shimura, Hideharu Amano:
Trax solver on Zynq with Deep Q-Network. FPT 2015: 272-275
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last updated on 2024-08-20 20:28 CEST by the dblp team
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