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Daewoong Lee
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2020 – today
- 2024
- [c5]Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sanghoon Kim, Daewoong Lee, Seongyeal Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gun-hee Cho, ChanYong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hong-Jun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, TaeHoon Park, Tae-Young Oh, Changsik Yoo, SangJoon Hwang:
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. ISSCC 2024: 242-244 - 2023
- [j6]Daewoong Lee
, Jaehyeok Baek, Hye-Jung Kwon, Daehyun Kwon, Chulhee Cho
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ. IEEE J. Solid State Circuits 58(1): 279-290 (2023) - 2022
- [c4]Daewoong Lee, Hye-Jung Kwon, Daehyun Kwon, Jaehyeok Baek, Chulhee Cho
A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus. ISSCC 2022: 446-448 - 2020
- [j5]Daewoong Lee
A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4: 1 CMOS Clockless Multiplexer. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 67-71 (2020)
2010 – 2019
- 2019
- [j4]Chongsoo Jung
A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1972-1976 (2019) - [j3]Daewoong Lee
A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 724-728 (2019) - [c3]Hyein Shin, Jaehyeong Sim
A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks. ICCAD 2019: 1-8 - [c2]Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim:
A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS. VLSI Circuits 2019: 196- - 2018
- [j2]Yong-Hun Kim
A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1539-1543 (2018) - [j1]Dongil Lee
A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1564-1568 (2018) - 2015
- [c1]Daewoong Lee, Dongil Lee, Taeho Lee, Yong-Hun Kim, Lee-Sup Kim:
An integrated time register and arithmetic circuit with combined operation for time-domain signal processing. ISCAS 2015: 1830-1833
Coauthor Index
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