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Keith A. Campbell
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2010 – 2019
- 2019
- [j4]Keith A. Campbell, Chen-Hsuan Lin, Deming Chen:
Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1056-1069 (2019) - [j3]Keith A. Campbell, David Lin, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Subhasish Mitra, Deming Chen:
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1345-1358 (2019) - 2018
- [c6]Keith A. Campbell, Chen-Hsuan Lin, Deming Chen:
Low-cost hardware architectures for mersenne modulo functional units. ASP-DAC 2018: 599-604 - 2017
- [b1]Keith A. Campbell:
Robust and reliable hardware accelerator design through high-level synthesis. University of Illinois Urbana-Champaign, USA, 2017 - [j2]Keith A. Campbell, Wei Zuo, Deming Chen:
New advances of high-level synthesis for efficient and reliable hardware design. Integr. 58: 189-214 (2017) - [c5]Eric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Q. Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz G. Szafaryn, Christos Vezyrtzis, Subhasish Mitra:
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. ICCD 2017: 593-596 - 2016
- [c4]Zelei Sun, Keith A. Campbell, Wei Zuo, Kyle Rupnow, Swathi T. Gurumani, Frederic Doucet, Deming Chen:
Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis. ASP-DAC 2016: 218-225 - [c3]Keith A. Campbell, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation. DAC 2016: 7:1-7:6 - 2015
- [j1]Zhiru Zhang, Deming Chen, Steve Dai, Keith A. Campbell:
High-level Synthesis for Low-power Design. IPSJ Trans. Syst. LSI Des. Methodol. 8: 12-25 (2015) - [c2]Keith A. Campbell, David Lin, Subhasish Mitra, Deming Chen:
Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles. DAC 2015: 53:1-53:6 - [c1]Keith A. Campbell, Pranay Vissa, David Z. Pan, Deming Chen:
High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths. DAC 2015: 161:1-161:6
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