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Chung-Shiang Wu
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2010 – 2019
- 2019
- [c6]Todd Takken, Andrew Ferencz, Chung-Shiang Wu, Liam McAuliffe, Tianyu Jia, Xin Zhang:
A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters (invited paper). VLSI Circuits 2019: 168- - 2018
- [j3]Chung-Shiang Wu
, Makoto Takamiya, Takayasu Sakurai:
Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1139-1150 (2018) - 2017
- [j2]Chung-Shiang Wu, Hui-Hsuan Lee, Po-Hung Chen
Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 783-787 (2017) - [c5]Chung-Shiang Wu, Makoto Takamiya, Takayasu Sakurai:
Buck converter with higher than 87% efficiency over 500nA to 20mA load current range for IoT sensor nodes by Clocked Hysteresis Control. CICC 2017: 1-4 - 2016
- [j1]Po-Hung Chen, Chung-Shiang Wu, Kai-Chun Lin:
A 50 nW-to-10 mW Output Power Tri-Mode Digital Buck Converter With Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting. IEEE J. Solid State Circuits 51(2): 523-532 (2016) - 2015
- [c4]Chung-Shiang Wu, Kai-Chun Lin, Yi-Ping Kuo, Po-Hung Chen, Yuan-Hua Chu, Wei Hwang:
An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications. ISCAS 2015: 1370-1373 - [c3]Po-Hung Chen, Chung-Shiang Wu, Kai-Chun Lin:
20.10 A 50nW-to-10mW output power tri-mode digital buck converter with self-tracking zero current detection for photovoltaic energy harvesting. ISSCC 2015: 1-3 - [c2]Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang:
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. VLSI-DAT 2015: 1-4 - 2014
- [c1]Pei-Chen Wu, Yi-Ping Kuo, Chung-Shiang Wu, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang:
PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. SoCC 2014: 136-139
Coauthor Index
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