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Srinivas Sabbavarapu
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2010 – 2019
- 2018
- [j4]Srinivas Sabbavarapu
, Basireddy Karunakar Reddy, Amit Acharyya:
Novel ASIC Design Flow Using Dynamic Libraries for Reducing Design Time. J. Low Power Electron. 14(2): 337-350 (2018) - [j3]Basireddy Karunakar Reddy, Srinivas Sabbavarapu
Cut-less Technology Mapping Using Shannon Factor Graph with on-the-fly Size Reduction. J. Low Power Electron. 14(3): 448-457 (2018) - 2017
- [j2]Srinivas Sabbavarapu
Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing. J. Low Power Electron. 13(3): 456-471 (2017) - 2014
- [j1]Srinivas Sabbavarapu
A Novel Integrated Circuit Design Methodology Using Dynamic Library Concept with Reduced Non-Recurring Engineering Cost and Time-to-Market. J. Low Power Electron. 10(3): 429-442 (2014) - [c5]Basireddy Karunakar Reddy, Srinivas Sabbavarapu
A new VLSI IC design automation methodology with reduced NRE costs and time-to-market using the NPN class Representation and functional symmetry. ISCAS 2014: 177-180 - [c4]Srinivas Sabbavarapu
A New Dynamic Library Based IC Design Automation Methodology Using Functional Symmetry with NPN Class Representation Approach to Reduce NRE Costs and Time-to-Market. ISED 2014: 115-119 - [c3]Basireddy Karunakar Reddy, Srinivas Sabbavarapu
Effect of Constant One and Zero, Shared and Non-decomposed Nodes on Runtime and Graph Size of the Shannon Factor Graph (SFG). ISED 2014: 135-139 - 2013
- [c2]Basireddy Karunakar Reddy, Srinivas Sabbavarapu
A Novel and Unified Digital IC Design and Automation Methodology with Reduced NRE Cost and Time-to-Market. ISED 2013: 36-40 - [c1]Srinivas Sabbavarapu
A Novel Physical Synthesis Methodology in the VLSI Design Automation by Introducing Dynamic Library Concept. ISED 2013: 103-107
Coauthor Index
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