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Tun Zainal Azni Zulkifli
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2020 – today
- 2020
- [j7]Furqan Zahoor
, Tun Zainal Azni Zulkifli
Carbon Nanotube and Resistive Random Access Memory Based Unbalanced Ternary Logic Gates and Basic Arithmetic Circuits. IEEE Access 8: 104701-104717 (2020) - [j6]Farooq Ahmad Khanday
Ultra-low-voltage integrable electronic implementation of delayed inertial neural networks for complex dynamical behavior using multiple activation functions. Neural Comput. Appl. 32(12): 8297-8314 (2020)
2010 – 2019
- 2019
- [j5]Farooq Ahmad Khanday
Low-Voltage Low-Power Integrable CMOS Circuit Implementation of Integer- and Fractional-Order FitzHugh-Nagumo Neuron Model. IEEE Trans. Neural Networks Learn. Syst. 30(7): 2108-2122 (2019) - 2017
- [j4]Sami Sattar, Tun Zainal Azni Zulkifli
A 2.4/5.2-GHz Concurrent Dual-Band CMOS Low Noise Amplifier. IEEE Access 5: 21148-21156 (2017) - 2014
- [j3]Ruhaifi Abdullah Zawawi, Tun Zainal Azni Zulkifli
A 1.6 ppm/°C bandgap voltage reference for an extended operating temperature range. IEICE Electron. Express 11(12): 20140383 (2014) - 2010
- [j2]Shukri Korakkottil Kunhi Mohd, Tun Zainal Azni Zulkifli
A general on-wafer noise figure de-embedding technique with gain uncertainty analysis. IEICE Electron. Express 7(4): 302-307 (2010) - [j1]Balasubramaniam Shammugasamy, Tun Zainal Azni Zulkifli
A 24mW, 5Gb/s fully balanced differential output trans-impedance amplifier with active inductor and capacitive degeneration techniques in 0.18µm CMOS technology. IEICE Electron. Express 7(4): 308-313 (2010)
2000 – 2009
- 2008
- [c2]Balasubramaniam Shammugasamy, Tun Zainal Azni Zulkifli
A 10-Gb/s fully balanced differential output transimpedance amplifier in 0.18-μm CMOS technology for SDH/SONET application. APCCAS 2008: 684-687 - 2006
- [c1]Harikrishnan Ramiah
Design of 3-4GHz Tunable Low Noise LC-QVCO for IEEE 802.11a WLAN Application. APCCAS 2006: 506-509
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