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Paris Kitsos
Paraskevas Kitsos
Person information
- affiliation: University of the Peloponnese, Electrical & Computer Engineering Department, Greece
- affiliation: Hellenic Open University, Patras, Greece
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2020 – today
- 2024
- [c57]Marios Papadopoulos, Kostas Lampropoulos, Paris Kitsos:
FPGA-Based Cloud Security Solutions for 5G Networks. CSR 2024: 913-918 - [c56]Aimilia Bantouna, Kostas Lampropoulos, Omar Qaise, Andreas Stamoulis, Paris Kitsos, Kostas Poulios, Lampros Raptis, Christos Tranoris:
SAND5G - Security Assessments for Networks and Services in 5G Networks. DSD 2024: 534-540 - 2023
- [j32]Stavros Kalapothas
, Manolis Galetakis, Georgios Flamis
A Survey on RISC-V-Based Machine Learning Ecosystem. Inf. 14(2): 64 (2023) - [j31]Constantinos Efstathiou, Ioannis Kouretas, Paris Kitsos:
On the modulo 2n+1 addition and subtraction for weighted operands. Microprocess. Microsystems 101: 104897 (2023) - [c55]Marios Papadopoulos, Paris Kitsos:
FPGA-Based Encryption System for Cloud Security. DSD 2023: 714-717 - [c54]Ludwig Kampel, Paris Kitsos, Dimitris E. Simos:
Summary of Locating Hardware Trojans using Combinatorial Testing for Cryptographic Circuits. ICSTW 2023: 260-262 - 2022
- [j30]Ludwig Kampel
Locating Hardware Trojans Using Combinatorial Testing for Cryptographic Circuits. IEEE Access 10: 18787-18806 (2022) - [j29]Stavros Kalapothas
Efficient Edge-AI Application Deployment for FPGAs. Inf. 13(6): 279 (2022) - [c53]Georgios Flamis, Stavros Kalapothas, Paris Kitsos:
FPGA-SoC Deployment of Complex Deep Neural Network for Magnitude and Phase Computations in Denoising of Speech Signal. VLSI-SoC 2022: 1-5 - 2021
- [j28]Constantinos Efstathiou, Paris Kitsos
Efficient majority logic magnitude comparator design. Microprocess. Microsystems 82: 103832 (2021) - [c52]Lampros Pyrgas, Paris Kitsos:
5G Security: FPGA Implementation of SNOW-V Stream Cipher. DSD 2021: 381-384 - [c51]Stavros Kalapothas, Georgios Flamis, Paris Kitsos
Importing Custom DNN Models on FPGAs. MECO 2021: 1-4 - [c50]Georgios Flamis, Stavros Kalapothas, Paris Kitsos:
Workflow on CNN utilization and inference in FPGA for embedded applications: 6th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM 2021). SEEDA-CECNSM 2021: 1-6 - 2020
- [j27]Filippos Pirpilidis, Lampros Pyrgas
8-bit serialised architecture of SEED block cipher for constrained devices. IET Circuits Devices Syst. 14(3): 316-321 (2020) - [c49]Lampros Pyrgas, Aliki Panagiotarou, Paris Kitsos
Are ring oscillators without a combinatorial loop good enough for Hardware Trojan detection? DSD 2020: 218-221
2010 – 2019
- 2019
- [j26]Apostolos P. Fournaris
An efficient multi-parameter approach for FPGA hardware Trojan detection. Microprocess. Microsystems 71 (2019) - [c48]Anastasios Fanariotis
DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education. DSD 2019: 152-159 - [c47]Lampros Pyrgas, Paris Kitsos
A Very Compact Architecture of CLEFIA Block Cipher for Secure IoT Systems. DSD 2019: 624-627 - [c46]Lampros Pyrgas, Paris Kitsos
An 8-bit Compact Architecture of Lesamnta-LW Hash Function for Constrained Devices. ICECS 2019: 743-746 - 2018
- [j25]Lampros Pyrgas
Compact FPGA architectures for the two-band fast discrete Hartley transform. Microprocess. Microsystems 61: 117-125 (2018) - [c45]Lampros Pyrgas
A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip Sensing. ARC 2018: 294-303 - [c44]Apostolos P. Fournaris, Lampros Pyrgas, Paris Kitsos
An FPGA Hardware Trojan Detection Approach Based on Multiple Parameter Analysis. DSD 2018: 516-522 - [c43]Filippos Pirpilidis, Lampros Pyrgas, Paris Kitsos
A 4-bit Architecture of SEED Block Cipher for IoT Applications. ICECS 2018: 389-392 - 2017
- [j24]João Canas Ferreira
MICPRO DSD 2015 special issue. Microprocess. Microsystems 52: 438 (2017) - [j23]Filippos Pirpilidis, Kyriakos G. Stefanidis
On the effects of ring oscillator length and hardware Trojan size on an FPGA-based implementation of AES. Microprocess. Microsystems 54: 75-82 (2017) - [c42]Lampros Pyrgas, Filippos Pirpilidis, Aliki Panayiotarou, Paris Kitsos
Thermal Sensor Based Hardware Trojan Detection in FPGAs. DSD 2017: 268-273 - [c41]Fotios Kounelis
Run-Time Effect by Inserting Hardware Trojans, in Combinational Circuits. DSD 2017: 287-290 - 2016
- [j22]Lilian Bossuet, Giorgio Di Natale, Paris Kitsos
Introduction to Special Issue on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE). Microprocess. Microsystems 47: 1-2 (2016) - [c40]Artemios G. Voyiatzis, Kyriakos G. Stefanidis
Efficient triggering of Trojan hardware logic. DDECS 2016: 200-205 - [c39]Paris Kitsos
TERO-Based Detection of Hardware Trojans on FPGA Implementation of the AES Algorithm. DSD 2016: 678-681 - [c38]Lambros Pyrgas, Paris Kitsos
An FPGA design for the Two-Band Fast Discrete Hartley Transform. ISSPIT 2016: 295-299 - [c37]Filippos Pirpilidis, Artemios G. Voyiatzis, Lambros Pyrgas, Paris Kitsos
An Efficient Reconfigurable Ring Oscillator for Hardware Trojan Detection. PCI 2016: 66 - [e1]Paris Kitsos:
2016 Euromicro Conference on Digital System Design, DSD 2016, Limassol, Cyprus, August 31 - September 2, 2016. IEEE Computer Society 2016, ISBN 978-1-5090-2817-7 [contents] - 2015
- [j21]Apostolos P. Fournaris, Ioannis Zafeirakis, Paris Kitsos
Comparing design approaches for elliptic curve point multiplication over GF(2k) with polynomial basis representation. Microprocess. Microsystems 39(8): 1139-1155 (2015) - [c36]Paris Kitsos
A Comparison of TERO and RO Timing Sensitivity for Hardware Trojan Detection Applications. DSD 2015: 547-550 - [c35]Paris Kitsos
Exciting FPGA cryptographic Trojans using combinatorial testing. ISSRE 2015: 69-76 - [c34]Filippos Pirpilidis, Paris Kitsos
A compact design of SEED block cipher. MECO 2015: 119-123 - 2014
- [j20]Seong-Lyun Kim, Paris Kitsos
Guest Editorial: Smart Grid Communications Systems. IEEE Syst. J. 8(2): 417-421 (2014) - [c33]Paris Kitsos
FPGA Trojan Detection Using Length-Optimized Ring Oscillators. DSD 2014: 675-678 - [c32]Athanasios Kakarountas
Cipher Text Stealing integrated in implementations of IEEE P1619 for shared storage media. ISCCSP 2014: 574-577 - [c31]Paris Kitsos
Towards a hardware Trojan detection methodology. MECO 2014: 18-23 - 2013
- [j19]Miguel Morales-Sandoval
Area/performance trade-off analysis of an FPGA digit-serial GF(2m)GF(2m) Montgomery multiplier based on LFSR. Comput. Electr. Eng. 39(2): 542-549 (2013) - [j18]Hana Kubátová, Paris Kitsos
Editorial of special issue: Digital System Safety and Security. Microprocess. Microsystems 37(2): 113-114 (2013) - [j17]Paris Kitsos
FPGA-based performance analysis of stream ciphers ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0. Microprocess. Microsystems 37(2): 235-245 (2013) - [c30]Filippos Pirpilidis, Paris Kitsos
An Efficient FPGA-Based Architecture of Skein for Simple Hashing and MAC Function. DSD 2013: 301-304 - [c29]Paris Kitsos
A high speed FPGA implementation of the 2D DCT for Ultra High Definition video coding. DSP 2013: 1-5 - 2012
- [j16]Paris Kitsos
A comparative study of hardware architectures for lightweight block ciphers. Comput. Electr. Eng. 38(1): 148-160 (2012) - [c28]George Provelengios, Paris Kitsos
FPGA-based Design Approaches of Keccak Hash Function. DSD 2012: 648-653 - [c27]Nicolas Sklavos
VLSI Design and Implementation of Homophonic Security System. ISVLSI 2012: 69-72 - [c26]Nicolas Sklavos
Architectural Optimizations & Hardware Implementations of WLANs Encryption Standard. NTMS 2012: 1-5 - 2011
- [j15]Miguel Morales-Sandoval
Bit-serial and digit-serial GF(2m)Montgomery multipliers using linear feedback shift registers. IET Comput. Digit. Tech. 5(2): 86-94 (2011) - [c25]George Provelengios, Nikolaos S. Voros
Low Power FPGA Implementations of JH and Fugue Hash Functions. DSD 2011: 417-421 - [c24]Paris Kitsos
An FPGA Implementation of the ZUC Stream Cipher. DSD 2011: 814-817 - [c23]Paris Kitsos
An FPGA implementation and performance evaluation of the seed block cipher. DSP 2011: 1-5 - [c22]Sotirios Kontogiannis
Snmp for Ethernet Networks SETH: A Network Benchmark Toolkit for Managing Routers Statistical Information. Panhellenic Conference on Informatics 2011: 175-179 - 2010
- [c21]Paris Kitsos
Low Power FPGA Implementations of 256-bit Luffa Hash Function. DSD 2010: 416-419 - [c20]Paris Kitsos
On the hardware implementation efficiency of SHA-3 candidates. ICECS 2010: 1240-1243 - [c19]Nicolas Sklavos, Paris Kitsos:
BLAKE HASH Function Family on FPGA: From the Fastest to the Smallest. ISVLSI 2010: 139-142
2000 – 2009
- 2009
- [j14]Jong Hyuk Park, Han-Chieh Chao, Whai-En Chen, Paris Kitsos
Editorial: Special Issue on "Information Security and Data Protection in Future Generation Communication and Networking". Wirel. Pers. Commun. 51(1): 1-3 (2009) - 2008
- [j13]Shiguo Lian, Yan Zhang, Jong Hyuk Park, Paris Kitsos:
Secure multimedia communication. Secur. Commun. Networks 1(6): 437-440 (2008) - [c18]Paris Kitsos
A Hardware Implementation of CURUPIRA Block Cipher for Wireless Sensors. DSD 2008: 850-853 - [p1]Joan Daemen, Paris Kitsos
The Self-synchronizing Stream Cipher Moustique. The eSTREAM Finalists 2008: 210-223 - 2007
- [j12]Paris Kitsos
Guest Editors' Introduction to the Special Issue on Security of Computers and Networks. Comput. Electr. Eng. 33(5-6): 321-323 (2007) - [j11]Paris Kitsos
UMTS security: system architecture and hardware implementation. Wirel. Commun. Mob. Comput. 7(4): 483-494 (2007) - [c17]Paris Kitsos
A high-speed hardware implementation of the Hermes8-128 stream cipher. ECCTD 2007: 364-367 - [c16]Paris Kitsos, Bhanu Prasad:
A System-on-Chip Design of the RadioGatún Hash Function. HPCNCS 2007: 231-237 - [c15]Paris Kitsos
An FPGA-based implementation of the Pomaranch stream cipher. MobiMedia 2007: 49 - 2006
- [j10]Paris Kitsos
Architectures and FPGA Implementations of the 64-Bit MISTY1 Block Cipher. J. Circuits Syst. Comput. 15(6): 817-831 (2006) - [j9]Nicolas Sklavos
Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security. J. Supercomput. 36(1): 33-50 (2006) - 2005
- [j8]Michalis D. Galanis, Paris Kitsos, Giorgos Kostopoulos, Nicolas Sklavos, Constantinos E. Goutis:
Comparison of the Hardware Implementation of Stream Ciphers. Int. Arab J. Inf. Technol. 2(4): 267-274 (2005) - [j7]Paris Kitsos
An Fpga Implementation of the Gprs Encryption Algorithm 3 (gea3). J. Circuits Syst. Comput. 14(2): 217-232 (2005) - [c14]Paris Kitsos
A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher. ISCAS (5) 2005: 4641-4644 - [c13]Odysseas G. Koufopavlou, George N. Selimis, Nicolas Sklavos, Paris Kitsos
Cryptography: Circuits and Systems Approach. PATMOS 2005: 750 - [i1]Paris Kitsos:
On the Hardware Implementation of the MICKEY-128 Stream Cipher. IACR Cryptol. ePrint Arch. 2005: 301 (2005) - 2004
- [j6]Paris Kitsos
64-bit Block ciphers: hardware implementations and comparison analysis. Comput. Electr. Eng. 30(8): 593-604 (2004) - [j5]Paris Kitsos, Odysseas G. Koufopavlou:
Configurable Hardware Implementations of Bulk Encryption Units for Wireless Communications. Int. Arab J. Inf. Technol. 1(1) (2004) - [j4]Nicolas Sklavos
Open Mobile Alliance (OMA) Security Layer: Architecture, Implementation and Performance Evaluation of the Integrity Unit. New Gener. Comput. 23(1): 77-100 (2004) - [j3]Paris Kitsos
Efficient architecture and hardware implementation of the Whirlpool hash function. IEEE Trans. Consumer Electron. 50(1): 208-213 (2004) - [c12]Michalis D. Galanis, Paris Kitsos, Giorgos Kostopoulos, Nicolas Sklavos, Odysseas G. Koufopavlou, Costas E. Goutis:
Comparison of the hardware architectures and FPGA implementations of stream ciphers. ICECS 2004: 571-574 - [c11]Georgios N. Selimis, Paris Kitsos, Odysseas G. Koufopavlou:
High performance cryptographic engine PANAMA: hardware implementation. ICECS 2004: 575-578 - [c10]Paris Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou:
High-speed hardware implementations of the KASUMI block cipher. ISCAS (2) 2004: 549-552 - [c9]Paris Kitsos, Odysseas G. Koufopavlou:
Whirlpool hash function: architecture and VLSI implementation. ISCAS (2) 2004: 893-896 - 2003
- [j2]Paris Kitsos
An efficient reconfigurable multiplier architecture for Galois field GF(2m). Microelectron. J. 34(10): 975-980 (2003) - [j1]Paraskevas Kitsos
Hardware Implementation of Bluetooth Security. IEEE Pervasive Comput. 2(1): 21-29 (2003) - [c8]Paris Kitsos
VLSI implementations of the triple-DES block cipher. ICECS 2003: 76-79 - [c7]Paris Kitsos
An reconfigurable multiplier in GF(2m) for elliptic curve cryptosystem. ICECS 2003: 699-702 - 2002
- [c6]Nicolas Sklavos
Euclidean algorithm VLSI implementations. ICECS 2002: 557-560 - [c5]Nicolas Sklavos
VLSI implementation of password (PIN) authentication unit. ICECS 2002: 1147-1150 - [c4]Paris Kitsos
An efficient implementation of the digital signature algorithm. ICECS 2002: 1151-1154 - [c3]Nicolas Sklavos, Paris Kitsos, Kyriakos Papadomanolakis, Odysseas G. Koufopavlou:
Random number generator architecture and VLSI implementation. ISCAS (4) 2002: 854-857 - [c2]Paris Kitsos, Nicolas Sklavos, Odysseas G. Koufopavlou:
Hardware implementation of the SAFER+ encryption algorithm for the Bluetooth system. ISCAS (4) 2002: 878-881 - 2001
- [c1]Paris Kitsos, Nicolas Sklavos, Nikolaos D. Zervas, Odysseas G. Koufopavlou:
A reconfigurable linear feedback shift register (LFSR) for the Bluetooth system. ICECS 2001: 991-994
Coauthor Index
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