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Payman Behnam
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2020 – today
- 2024
- [c23]Alind Khare, Animesh Agrawal, Aditya Annavajjala, Payman Behnam, Myungjin Lee, Hugo Latapie, Alexey Tumanov:
SuperFedNAS: Cost-Efficient Federated Neural Architecture Search for On-device Inference. ECCV (79) 2024: 161-179 - [c22]Payman Behnam, Uday Kamal, Ali Shafiee, Alexey Tumanov, Saibal Mukhopadhyay:
Harmonica: Hybrid Accelerator to Overcome Imperfections of Mixed-signal DNN Accelerators. IPDPS 2024: 619-630 - [i7]Bingbing Li, Geng Yuan, Zigeng Wang, Shaoyi Huang, Hongwu Peng, Payman Behnam, Wujie Wen, Hang Liu, Caiwen Ding:
Zero-Space Cost Fault Tolerance for Transformer-based Language Models on ReRAM. CoRR abs/2401.11664 (2024) - 2023
- [j8]Payman Behnam
, Jianming Tong, Alind Khare, Yangyu Chen, Yue Pan
Hardware-Software Co-Design for Real-Time Latency-Accuracy Navigation in Tiny Machine Learning Applications. IEEE Micro 43(6): 93-101 (2023) - [c21]Payman Behnam, Alexey Tumanov, Tushar Krishna, Pranav Gadikar, Yangyu Chen, Jianming Tong, Yue Pan, Abhimanyu Rajeshkumar Bambhaniya, Alind Khare:
Subgraph Stationary Hardware-Software Inference Co-Design. MLSys 2023 - [i6]Payman Behnam, Jianming Tong, Alind Khare, Yangyu Chen, Yue Pan, Pranav Gadikar, Abhimanyu Rajeshkumar Bambhaniya, Tushar Krishna, Alexey Tumanov:
Subgraph Stationary Hardware-Software Inference Co-Design. CoRR abs/2306.17266 (2023) - [i5]Anshul Ahluwalia, Rohit Das, Payman Behnam, Alind Khare, Pan Li, Alexey Tumanov:
ABKD: Graph Neural Network Compression with Attention-Based Knowledge Distillation. CoRR abs/2310.15938 (2023) - 2022
- [j7]Payman Behnam
Adaptively Reduced DRAM Caching for Energy-Efficient High Bandwidth Memory. IEEE Trans. Computers 71(10): 2675-2686 (2022) - [j6]Behnam Khodabandeloo, Ahmad Khonsari
Stereo: Assignment and Scheduling in MPSoC Under Process Variation by Combining Stochastic and Decomposition Approaches. IEEE Trans. Computers 71(11): 2940-2954 (2022) - [c20]Yixuan Luo, Payman Behnam, Kiran Thorat, Zhuo Liu, Hongwu Peng
CoDG-ReRAM: An Algorithm-Hardware Co-design to Accelerate Semi-Structured GNNs on ReRAM. ICCD 2022: 280-289 - [i4]Payman Behnam, Uday Kamal, Saibal Mukhopadhyay:
An Algorithm-Hardware Co-design Framework to Overcome Imperfections of Mixed-signal DNN Accelerators. CoRR abs/2208.13896 (2022) - 2021
- [c19]Geng Yuan, Payman Behnam, Yuxuan Cai, Ali Shafiee, Jingyan Fu, Zhiheng Liao, Zhengang Li, Xiaolong Ma, Jieren Deng, Jinhui Wang, Mahdi Nazm Bojnordi, Yanzhi Wang, Caiwen Ding:
TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators. DATE 2021: 926-931 - [c18]Geng Yuan, Payman Behnam, Zhengang Li, Ali Shafiee, Sheng Lin, Xiaolong Ma, Hang Liu, Xuehai Qian, Mahdi Nazm Bojnordi, Yanzhi Wang, Caiwen Ding:
FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator. ISCA 2021: 265-278 - [i3]Geng Yuan, Payman Behnam, Zhengang Li, Ali Shafiee, Sheng Lin, Xiaolong Ma, Hang Liu, Xuehai Qian, Mahdi Nazm Bojnordi, Yanzhi Wang, Caiwen Ding:
FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator. CoRR abs/2106.09144 (2021) - 2020
- [j5]Payman Behnam
STFL-DDR: Improving the Energy-Efficiency of Memory Interface. IEEE Trans. Computers 69(12): 1823-1834 (2020) - [c17]Payman Behnam, Mahdi Nazm Bojnordi:
RedCache: Reduced DRAM Caching. DAC 2020: 1-6
2010 – 2019
- 2019
- [c16]Payman Behnam, Mahdi Nazm Bojnordi:
STFL: Energy-Efficient Data Movement with Slow Transition Fast Level Signaling. DAC 2019: 42 - [c15]Sajjad Taheri, Payman Behnam, Eli Bozorgzadeh, Alexander V. Veidenbaum, Alexandru Nicolau:
AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms. FPGA 2019: 252-261 - 2018
- [j4]Yomi Karthik Rupesh, Payman Behnam, Goverdhan Reddy Pandla, Manikanth Miryala, Mahdi Nazm Bojnordi
Accelerating k-Medians Clustering Using a Novel 4T-4R RRAM Cell. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2709-2722 (2018) - [c14]Sajjad Taheri, Jin Heo, Payman Behnam, Jeffrey Chen, Alexander V. Veidenbaum, Alexandru Nicolau:
Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines. FCCM 2018: 227 - [c13]Payman Behnam, Arjun Pal Chowdhury, Mahdi Nazm Bojnordi:
R-Cache: A Highly Set-Associative In-Package Cache Using Memristive Arrays. ICCD 2018: 423-430 - [i2]Payman Behnam:
Validation of Hardware Security and Trust: A Survey. CoRR abs/1801.00649 (2018) - 2017
- [c12]Farzaneh Zokaee, Hossein Sabaghian Bidgoli, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi:
A novel SAT-based ATPG approach for transition delay faults. HLDVT 2017: 17-22 - [c11]Hossein Sabaghian Bidgoli, Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi:
Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach. ISVLSI 2017: 545-550 - [c10]Payman Behnam, Naser Sedaghati, Mahdi Nazm Bojnordi:
Adaptive Time-based Encoding for Energy-Efficient Large Cache Architectures. E2SC@SC 2017: 5:1-5:8 - [i1]Payman Behnam, Bijan Alizadeh, Sajjad Taheri:
Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs. CoRR abs/1712.09818 (2017) - 2016
- [j3]Eesa Nikahd
High-Speed Hardware Implementation of Fixed and Runtime Variable Window Length 1-D Median Filters. IEEE Trans. Circuits Syst. II Express Briefs 63-II(5): 478-482 (2016) - [c9]Payman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita:
Formally analyzing fault tolerance in datapath designs using equivalence checking. ASP-DAC 2016: 133-138 - 2015
- [j2]Bijan Alizadeh, Payman Behnam, Somayeh Sadeghi Kohan:
A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Trans. Computers 64(6): 1564-1578 (2015) - [c8]Payman Behnam, Bijan Alizadeh:
In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms. ATS 2015: 199-204 - 2014
- [c7]Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi:
Automatic correction of certain design errors using mutation technique. ETS 2014: 1-2 - [c6]Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi:
Improving polynomial datapath debugging with HEDs. ETS 2014: 1-6 - [c5]Vahid Janfaza, Bahjat Forouzandeh, Payman Behnam, Mohammadreza Najafi:
Hybrid history-based test overlapping to reduce test application time. EWDTS 2014: 1-4 - [c4]Vahid Janfaza, Payman Behnam, Bahjat Forouzandeh, Bijan Alizadeh:
A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression. ISVLSI 2014: 220-225 - [c3]M. H. Haghbayan, Bijan Alizadeh, Payman Behnam, Saeed Safari
Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism. VLSID 2014: 80-85 - 2013
- [j1]Bijan Alizadeh, Payman Behnam:
Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs. Microprocess. Microsystems 37(8-D): 1108-1121 (2013) - [c2]Payman Behnam, Hossein Sabaghian Bidgoli, Bijan Alizadeh, Kamyar Mohajerani, Zainalabedin Navabi:
A probabilistic approach for counterexample generation to aid design debugging. EWDTS 2013: 1-5 - [c1]Vahid Janfaza, Bahjat Forouzandeh, Payman Behnam, Mohammadreza Najafi:
Hybrid history-based test overlapping to reduce test application time. EWDTS 2013: 1-4
Coauthor Index
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