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Jau-Ji Jou

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2020 – today

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2023
[c12]
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Chao-Ho Chen, Tsong-Yi Chen, Yong-Lin Chen, Bing-Hong Liu, Jau-Ji Jou, Cheng-Kang Wen:
The Abnormal Events Detection System by Feature Enhancement-Based Deep Learning Network. GCCE 2023: 417-418
2022
[j2]
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Jau-Ji Jou, Tien-Tsorng Shih, Hao-Wen Hsu:
32-Gb/s NRZ and 40-Gb/s PAM-4 Transimpedance Amplifier Paralleling with a Differentiator for Bandwidth Enhancement in 90-nm CMOS Technology. Circuits Syst. Signal Process. 41(2): 621-635 (2022)
[c11]
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Vinh V. Le, Dung H. P. Nguyen, Bing-Hong Liu, Shao-I Chu, Chih-Yuan Lien, Jau-Ji Jou:
An Algorithm Design for Minimum-Latency Scheduling in Multiple-Data-Type Multi-Channel WSNs. GCCE 2022: 810-811
[c10]
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C. L. Chiu, Ting-Rong Chen, Chia-Wei Lee, Jau-Ji Jou:
The Study of 60 GHz Wideband Conductor-Backed Coplanar Waveguide on a TGV Substrate. GCCE 2022: 816-817
2021
[c9]
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Hao-Wen Hsu, Xuan-Yi Ye, Jau-Ji Jou, Tien-Tsorng Shih:
A 40-Gb/s NRZ Inductorless Transimpedance Amplifier in a 0.18-μm SiGe BiCMOS Technology. ISPACS 2021: 1-2
[c8]
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Chun-Chen Yao, Jun-Yuan Zheng, Jau-Ji Jou, Chun-Liang Yang:
Performance Monitoring of High-Speed NRZ Signals Using Machine Learning Techniques. ISPACS 2021: 1-2

2010 – 2019

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2019
[c7]
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Hao-Wen Hsu, Chih-Chen Peng, Jau-Ji Jou, Tien-Tsorng Shih, Yaw-Dung Wu, Shao-I Chu, Chih-Yuan Lien, Bing-Hong Liu:
25 Gb/s NRZ and 50 Gb/s PAM-4 Transimpedance Amplifier with Active Feedback and Equalization in 90 nm CMOS Technology. ICETE (1) 2019: 257-263
[c6]
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Jian-Yu Lai, Chuan-Yu Liao, Jau-Ji Jou, Tien-Tsorng Shih, Po-Jui Chiang:
Design of High-Speed Optical Receiver Module for 160Gb/s NRZ and 200Gb/s PAM4 Transmissions. ISCAS 2019: 1-4
[c5]
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Tsung-Yen Wu, Jau-Ji Jou, Tien-Tsorng Shih, Po-Jui Chiang, Yaw-Dung Wu:
Design of a 25-Gb/s PAM-4 VCSEL Diode Driver with an Equalizer in 90-nm CMOS Technology. ISCAS 2019: 1-4
2017
[c4]
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Chih-Chen Peng, Jau-Ji Jou, Tien-Tsorng Shih, Chien-Liang Chiu:
High linearity transimpedance amplifier in 0.18-μm CMOS technology for 20-Gb/s PAM-4 receivers. ISOCC 2017: 182-183
[c3]
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Chi-Hsien Wu, Jau-Ji Jou, Hsin-Wen Ting, Shao-I Chu, Bing-Hong Liu:
Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology. ISOCC 2017: 276-277
[c2]
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Hsuan-Yun Kao, Cheng-Ting Tsai, Chun-Yen Pong, Shan-Fong Liang, Zu-Kai Weng, Yu-Chieh Chi, Hao-Chung Kuo, Jian Jang Huang, Tai-Cheng Lee, Tien-Tsorng Shih, Jau-Ji Jou, Wood-Hi Cheng, Chao-Hsin Wu, Gong-Ru Lin:
Few-mode 850-nm VCSEL chip with direct 16-QAM OFDM encoding at 80-Gbit/s for 100-m OM4 MMF link. OFC 2017: 1-3
2016
[c1]
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Hong-Jhih Chen, Jau-Ji Jou, Tien-Tsorng Shih:
Design of pseudo-random bit sequence generator with adjustable sinusoidal jitter. ISOCC 2016: 263-264

2000 – 2009

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2002
[j1]
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Jau-Ji Jou, Cheng-Kuang Liu:
Application of SPICE simulation to study WDM and SCM systems using EDFAs with chirping. IEEE Trans. Educ. 45(3): 238-244 (2002)

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