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Johan Wernehag
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2010 – 2019
- 2018
- [c8]Therese Forsberg, Johan Wernehag, Henrik Sjöland
, Markus Törmänen:
A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOS. NORCAS 2018: 1-4 - 2017
- [j2]Imad ud Din
Two Tunable Frequency Duplexer Architectures for Cellular Transceivers. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(11): 2988-2999 (2017) - 2016
- [c7]Tobias Tired, Henrik Sjöland
Comparison of two SiGe 2-stage E-band power amplifier architectures. APCCAS 2016: 666-669 - [c6]Johan Wernehag, Waqas Ahmad, Henrik Sjöland
A 30dBm PA for MTC communication in 65nm CMOS technology. LASCAS 2016: 147-150 - 2015
- [c5]Navneeta Deo, Johan Wernehag, Joakim Thelberg:
Low power, highly stable and wideband LNA for GNSS applications in SiGe technology. NORCAS 2015: 1-4 - 2014
- [c4]Tobias Tired, Henrik Sjöland
A 28 GHz SiGe QVCO and divider for an 81-86 GHz E-band beam steering transmitter PLL. NORCHIP 2014: 1-4 - 2013
- [j1]Imad ud Din, Johan Wernehag, Stefan Back Andersson, Sven Mattisson, Henrik Sjöland
Wideband SAW-Less Receiver Front-End With Harmonic Rejection Mixer in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 60-II(5): 242-246 (2013) - 2012
- [c3]Imad ud Din, Johan Wernehag, Stefan Back Andersson, Sven Mattisson:
Wideband Reconfigurable Capacitive shunt-feedback LNA in 65nm CMOS. NORCHIP 2012: 1-4 - 2011
- [c2]Xiaodong Liu, Vijay Viswam, Stefan Back Andersson, Johan Wernehag, Imad ud Din, Pietro Andreani:
Highly linear direct conversion receiver using customized on-chip balun. NORCHIP 2011: 1-4
2000 – 2009
- 2008
- [c1]Johan Wernehag, Henrik Sjöland
60 GHz 130-nm CMOS second harmonic power amplifiers. APCCAS 2008: 300-303
Coauthor Index
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