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Clifford Wolf
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2010 – 2019
- 2019
- [c6]David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic:
Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs. FCCM 2019: 1-4 - [i1]David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic:
Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs. CoRR abs/1903.10407 (2019) - 2018
- [c5]Aina Niemetz
, Mathias Preiner
Btor2 , BtorMC and Boolector 3.0. CAV (1) 2018: 587-595 - 2017
- [c4]Christian Krieg, Clifford Wolf, Axel Jantsch
Toggle MUX: How X-Optimism Can Lead to Malicious Hardware. DAC 2017: 7:1-7:6 - 2016
- [c3]Christian Krieg, Clifford Wolf, Axel Jantsch
Malicious LUT: a stealthy FPGA trojan injected and triggered by the design flow. ICCAD 2016: 43 - 2012
- [c2]Clifford Wolf, Johann Glaser, Florian Schupfer, Jan Haase, Christoph Grimm:
Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic. FDL 2012: 194-201 - [c1]Johann Glaser, Clifford Wolf:
Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures. FDL (Selected Papers) 2012: 201-221
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last updated on 2024-04-25 05:51 CEST by the dblp team
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