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Xi Wang 0009
Person information
- affiliation: Texas Tech University, Lubbock, Texas, USA
Other persons with the same name
- Xi Wang — disambiguation page
- Xi Wang 0001 — Fujitsu Laboratories of America, Richardson, TX, USA (and 1 more)
- Xi Wang 0002 — Max-Delbrück-Center for Molecular Medicine, Berlin, Germany (and 2 more)
- Xi Wang 0003 — Ocean University of China, Qingdao, Shandong, China
- Xi Wang 0004 — National University of Singapore, Department of Electrical and Computer Engineering, Singapore
- Xi Wang 0005 — University of Washington, Seattle, WA, USA (and 1 more)
- Xi Wang 0006 — Soochow University, Suzhou, China (and 1 more)
- Xi Wang 0007 — Donghua University, Shanghai, China
- Xi Wang 0008 — Fudan University, Shanghai, China
- Xi Wang 0010 — Central University of Finance and Economics, Beijing, China (and 1 more)
- Xi Wang 0011 — University of Houston, TX, USA
- Xi Wang 0012 — University of Sheffield, UK (and 2 more)
- Xi Wang 0013 — Chinese University of Hong Kong, Department of Computer Science and Engineering, Hong Kong (and 1 more)
- Xi Wang 0014 — University of Chinese Academy of Sciences, Beijing, China (and 1 more)
- Xi Wang 0015 — Xidian University, School of Electro-Mechanical Engineering, Xi'an, China (and 1 more)
- Xi Wang 0016 — Microsoft Cloud and AI, Bejing, China
- Xi Wang 0017 — Shanghai University, School of Computer Engineering and Science, China (and 1 more)
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2020 – today
- 2024
- [j4]Cai Li, Haochang Zhi, Kaiyue Yang, Junyi Qian, Zhihao Yan, Lixuan Zhu, Chao Chen, Xi Wang, Weiwei Shan:
A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN. IEEE J. Solid State Circuits 59(3): 867-877 (2024) - [j3]Yuxuan Du, Junyi Qian, Zhengguo Shen, Chengjun Wu, Weiwei Shan, Xi Wang:
DSC-TRCP: Dynamically Self-Calibrating Tunable Replica Critical Paths Based Timing Monitoring for Variation Resilient Circuits. IEEE J. Solid State Circuits 59(7): 2286-2296 (2024) - [c21]Yuchen Hu, Ke Xu, Jialin Sun, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang:
Make Each Iteration Count. ACM TUR-C 2024 - [c20]Xi Wang, Gwok-Waa Wan, Sam-Zaak Wong, Layton Zhang, Tianyang Liu, Qi Tian, Jianmin Ye:
ChatCPU: An Agile CPU Design and Verification Platform with LLM. DAC 2024: 212:1-212:6 - [c19]Gwok-Waa Wan, Sam-Zaak Wong, Xi Wang:
Jailbreaking Pre-trained Large Language Models Towards Hardware Vulnerability Insertion Ability. ACM Great Lakes Symposium on VLSI 2024: 579-582 - [i2]Ning Wang, Bingkun Yao, Jie Zhou, Xi Wang, Zhe Jiang, Nan Guan:
Large Language Model for Verilog Generation with Golden Code Feedback. CoRR abs/2407.18271 (2024) - [i1]Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, Nan Guan:
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog. CoRR abs/2409.15186 (2024) - 2023
- [c18]Tao Xu, Xi Wang, Jianping He:
Differential Game with Mixed Strategies: A Weak Approximation Approach. CDC 2023: 5216-5221 - 2021
- [j2]Xi Wang, Antonino Tumeo, John D. Leidel, Jie Li, Yong Chen:
HAM: Hotspot-Aware Manager for Improving Communications With 3D-Stacked Memory. IEEE Trans. Computers 70(6): 833-848 (2021) - [c17]Zach Hansen, Brody Williams, John D. Leidel, Xi Wang, Yong Chen:
DMM-GAPBS: Adapting the GAP Benchmark Suite to a Distributed Memory Model. HPEC 2021: 1-8 - [c16]Xi Wang, John D. Leidel, Brody Williams, Alan Ehret, Miguel Mark, Michel A. Kinsy, Yong Chen:
xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing. IPDPS 2021: 454-463 - [c15]Brody Williams, John D. Leidel, Xi Wang, David Donofrio, Yong Chen:
CircusTent: A Tool for Measuring the Performance of Atomic Memory Operations on Emerging Architectures. OpenSHMEM 2021: 92-110 - 2020
- [j1]John D. Leidel, Xi Wang, Brody Williams, Yong Chen:
Toward a Microarchitecture for Efficient Execution of Irregular Applications. ACM Trans. Parallel Comput. 7(4): 26:1-26:24 (2020) - [c14]Xi Wang, Brody Williams, John D. Leidel, Alan Ehret, Michel A. Kinsy, Yong Chen:
Remote Atomic Extension (RAE) for Scalable High Performance Computing. DAC 2020: 1-6 - [c13]Xi Wang, John D. Leidel, Brody Williams, Yong Chen:
PAC: Paged Adaptive Coalescer for 3D-Stacked Memory. HPDC 2020: 137-148 - [c12]Brody Williams, John D. Leidel, Xi Wang, David Donofrio, Yong Chen:
CircusTent: A Benchmark Suite for Atomic Memory Operations. MEMSYS 2020: 144-157
2010 – 2019
- 2019
- [c11]Xi Wang, Jie Li, Antonino Tumeo, John D. Leidel, Yong Chen:
POSTER: Memory Hotspot Optimization for Data-Intensive Applications. PACT 2019: 467-468 - [c10]Xi Wang, Antonino Tumeo, John D. Leidel, Jie Li, Yong Chen:
MAC: Memory Access Coalescer for 3D-Stacked Memory. ICPP 2019: 2:1-2:10 - [c9]Brody Williams, Xi Wang, John D. Leidel, Yong Chen:
Collective Communication for the RISC-V xBGAS ISA Extension. ICPP Workshops 2019: 17:1-17:10 - [c8]Jie Li, Xi Wang, Antonino Tumeo, Brody Williams, John D. Leidel, Yong Chen:
PIMS: a lightweight processing-in-memory accelerator for stencil computations. MEMSYS 2019: 41-52 - 2018
- [c7]John D. Leidel, Xi Wang, Yong Chen:
GoblinCore-64: A RISC-V Based Architecture for Data Intensive Computing. HPEC 2018: 1-8 - [c6]Xi Wang, John D. Leidel, Yong Chen:
Memory Coalescing for Hybrid Memory Cube. ICPP 2018: 62:1-62:10 - [c5]John D. Leidel, Xi Wang, Frank Conlon, Yong Chen, David Donofrio, Farzad Fatollahi-Fard, Kurt Keville:
xBGAS: Toward a RISC-V ISA Extension for Global, Scalable Shared Memory. MCHPC@SC 2018: 22-26 - 2017
- [c4]Farzad Fatollahi-Fard, David Donofrio, John Shalf, John D. Leidel, Xi Wang, Yong Chen:
OpenSoC system architect: An open toolkit for building soft-cores on FPGAs. FPL 2017: 1 - [c3]Xi Wang, John D. Leidel, Yong Chen:
OpenMP Memkind: An Extension for Heterogeneous Physical Memories. ICPP Workshops 2017: 220-227 - [c2]John D. Leidel, Xi Wang, Yong Chen:
Pressure-Driven Hardware Managed Thread Concurrency for Irregular Applications. IA3@SC 2017: 7:1-7:8 - 2016
- [c1]Xi Wang, John D. Leidel, Yong Chen:
Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture. MEMSYS 2016: 177-187
Coauthor Index
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last updated on 2024-12-22 19:01 CET by the dblp team
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