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Rajat Chauhan
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2020 – today
- 2021
- [c11]Ashutosh Chitnis, Rajat Chauhan, Divya Kaur, Qadeer Khan:
A 0.75-5V, 15.8 nA with 1.8 μs Delay Supply Voltage Supervisor using Adaptively Biased Comparator and Sample & Hold Technique for IoT. CICC 2021: 1-2 - [c10]Vipul Singhal, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod
, Mahesh Mehendale, Anantha P. Chandrakasan:
150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications. VLSID 2021: 169-174
2010 – 2019
- 2019
- [j2]Satyasai Jagannath Nanda
A K-Means-Galactic Swarm Optimization-Based Clustering Algorithm with Otsu's Entropy for Brain Tumor Detection. Appl. Artif. Intell. 33(2): 152-170 (2019) - [j1]Sundeep Javvaji
Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting. IEEE J. Solid State Circuits 54(9): 2590-2600 (2019) - 2018
- [c9]Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, Shanthi Pavan:
Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting. ESSCIRC 2018: 42-45 - [c8]Rajat Chauhan, Nicholas C. Allen, Robert S. Keynton, Paula J. Bates, Mohammed T. Malik, Martin G. O. Toole:
Engineering sequence and stimuli dependent doxorubicin release from anti-nucleolin aptamer coated gold nanoparticles. ISSPIT 2018: 114-117 - [c7]Nagwa ElBaz, Rajat Chauhan, Kurtis T. James, Danial A. Malik
Gold Nanoparticles Conjugate Cancer-Targeting Aptamer and Gadolinium Chelate for MR Cancer Imaging. ISSPIT 2018: 520-525 - [c6]R. R. Manikandan, Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale:
A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. VLSID 2018: 171-176 - [c5]Sowmya Sankaranarayanan, Kulkarni Chaitali Vinod, Aswanth Sreekumar, Tonse Laxminidhi, Vipul Singhal, Rajat Chauhan:
Single Inductor Dual Output Buck Converter for Low Power Applications and Its Stability Analysis. VLSID 2018: 347-352 - 2015
- [c4]Rajat Chauhan, Prajkta Vyavahare, Siva Kothamasu:
Fail-safe I/O to control RESET# pin of DDR3 SDRAM and achieve ultra-low system power. ISQED 2015: 357-360 - 2013
- [c3]Rajat Chauhan, Manigandan Selvam:
Input Referred Offset Reduction in Very High Speed Differential Receivers. VLSI Design 2013: 115-119
2000 – 2009
- 2008
- [c2]Ankur Gupta, Rajat Chauhan, Vinod Menezes, Vikas Narang, H. M. Roopashree:
A Robust Level-Shifter Design for Adaptive Voltage Scaling. VLSI Design 2008: 383-388 - 2005
- [c1]Rajat Chauhan, Karthik Rajagopal, Vinod Menezes, H. M. Roopashree, Sanish Koshy Jacob:
A high performance, high voltage output buffer in a low voltage CMOS process. CICC 2005: 227-230
Coauthor Index
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